D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 379

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

7.5.14
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and DTME bit are
set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 7.35 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
7.5.15
If the DTE bit in DMABCRL is cleared to 0 for the channel currently operating, the DMAC stops
on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the
DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit in DMABCRL.
Figure 7.36 shows the procedure for forcibly terminating DMAC operation by software.
Figure 7.35 Example of Procedure for Continuing Transfer on Channel Interrupted
Forced Termination of DMAC Operation
DMAC and NMI Interrupts
transfer on interrupted
Transfer continues
Set DTME bit to 1
Resumption of
DTME = 0
DTE = 1
channel
Yes
No
[1]
[2]
by NMI Interrupt
Transfer ends
Rev. 3.00 Mar 17, 2006 page 327 of 926
Section 7 DMA Controller (DMAC)
[1]
[2]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
Write 1 to the DTME bit.
REJ09B0283-0300