D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 883

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

22.2.6
When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip
peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF), or for all the on-chip
peripheral functions except the 8-bit timer (MSTPCR = H'FFFE), executing a SLEEP instruction
while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions
(except the 8-bit timer and watchdog timer), the bus controller, and the I/O ports to stop operating,
and a transition to be made to all-module-clocks-stop mode, at the end of the bus cycle.
Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit.
All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ15 pins), RES
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
22.3
Output of the clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the clock stops at the end of the bus cycle,
and output goes high. clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, clock output is disabled and input port mode is set.
Table 22.3 shows the state of the pin in each processing state.
Table 22.3
DDR
0
1
1
PSTOP
X
0
1
Register Setting
All-Module-Clocks-Stop Mode
Clock Output Control
Normal
operating state
High impedance High impedance
Fixed high
Pin State in Each Processing State
output
Sleep mode
Fixed high
output
Software
standby mode
High impedance High impedance High impedance
Fixed high
Fixed high
Rev. 3.00 Mar 17, 2006 page 831 of 926
Hardware
standby mode
High impedance
High impedance Fixed high
Section 22 Power-Down Modes
REJ09B0283-0300
All-module-
clocks-stop mode
output