D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 335

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
7.3.6
The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the
transfer ended using a DTC chain transfer, and then reactivate the DTC. DMAWER applies
restrictions for changing all bits of DMACR, and specific bits for DMATCR and DMABCR for
the specific channel, to prevent inadvertent rewriting of registers other than those for the channel
concerned. The restrictions applied by DMAWER are valid for the DTC.
Figure 7.2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt
request, and reactivating channel 0A. The address register and count register areas are set again
during the first DTC transfer, then the control register area is set again during the second DTC
Bit
7
to
4
3
2
1
0
Bit Name
WE1B
WE1A
WE0B
WE0A
DMA Write Enable Register (DMAWER)
Initial Value
All 0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
Description
Reserved
These bits are always read as 0 and cannot be
modified.
Write Enable 1B
Enables or disables writes to all bits in
DMACR1B, bits 11, 7, and 3 in DMABCR, and
bit 5 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 1A
Enables or disables writes to all bits in
DMACR1A, and bits 10, 6, and 2 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0B
Enables or disables writes to all bits in
DMACR0B, bits 9, 5, and 1 in DMABCR, and bit
4 in DMATCR.
0: Writes are disabled
1: Writes are enabled
Write Enable 0A
Enables or disables writes to all bits in
DMACR0A, and bits 8, 4, and 0 in DMABCR.
0: Writes are disabled
1: Writes are enabled
Rev. 3.00 Mar 17, 2006 page 283 of 926
Section 7 DMA Controller (DMAC)
REJ09B0283-0300

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