D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 42

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Figure 15.9
Figure 15.10 Example of Communication Using Multiprocessor Format
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart....................................... 704
Figure 15.12 Example of SCI Operation in Reception
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (1) ...................................... 707
Figure 15.13 Sample Multiprocessor Serial Reception Flowchart (2) ...................................... 708
Figure 15.14 Data Format in Clocked Synchronous Communication (For LSB-First)............. 709
Figure 15.15 Sample SCI Initialization Flowchart.................................................................... 710
Figure 15.16 Sample SCI Transmission Operation in Clocked Synchronous Mode................. 712
Figure 15.17 Sample Serial Transmission Flowchart................................................................ 713
Figure 15.18 Example of SCI Operation in Reception.............................................................. 714
Figure 15.19 Sample Serial Reception Flowchart ..................................................................... 715
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations..... 717
Figure 15.21 Schematic Diagram of Smart Card Interface Pin Connections ............................ 718
Figure 15.22 Normal Smart Card Interface Data Format.......................................................... 719
Figure 15.23 Direct Convention (SDIR = SINV = O/E = 0)..................................................... 719
Figure 15.24 Inverse Convention (SDIR = SINV = O/E = 1) ................................................... 720
Figure 15.25 Receive Data Sampling Timing in Smart Card Mode
Figure 15.26 Retransfer Operation in SCI Transmit Mode ....................................................... 724
Figure 15.27 TEND Flag Generation Timing in Transmission Operation ................................ 724
Figure 15.28 Example of Transmission Processing Flow ......................................................... 725
Figure 15.29 Retransfer Operation in SCI Receive Mode......................................................... 726
Figure 15.30 Example of Reception Processing Flow .............................................................. 727
Figure 15.31 Timing for Fixing Clock Output Level ................................................................ 728
Figure 15.32 Clock Halt and Restart Procedure........................................................................ 729
Figure 15.33 Block Diagram of IrDA ....................................................................................... 730
Figure 15.34 IrDA Transmit/Receive Operations ..................................................................... 731
Figure 15.35 Example of Synchronous Transmission Using DTC ........................................... 737
Figure 15.36 Sample Flowchart for Mode Transition during Transmission ............................. 738
Figure 15.37 Port Pin States during Mode Transition
Figure 15.38 Port Pin States during Mode Transition
Figure 15.39 Sample Flowchart for Mode Transition during Reception................................... 740
Section 16 A/D Converter
Figure 16.1
Figure 16.2
Rev. 3.00 Mar 17, 2006 page xl of l
Sample Serial Reception Data Flowchart (2)....................................................... 701
(Transmission of Data H'AA to Receiving Station A)......................................... 703
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) ............................ 706
(Using Clock of 372 Times the Bit Rate)............................................................. 721
(Internal Clock, Asynchronous Transmission)..................................................... 739
(Internal Clock, Synchronous Transmission)....................................................... 739
Block Diagram of A/D Converter ........................................................................ 742
A/D Conversion Timing ...................................................................................... 754