D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 201

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

6.3.10
REFCR specifies DRAM/synchronous DRAM interface refresh control.
Note: The synchronous DRAM interface is not supported in the H8S/2678 Group.
Note:
Bit
15
14
13
12
* Only 0 can be written, to clear the flag.
Bit Name
CMF
CMIE
RCW1
RCW0
Refresh Control Register (REFCR)
Initial Value
0
0
0
0
R/W
R/(W) *
R/W
R/W
R/W
Description
Compare Match Flag
Status flag that indicates a match between the
values of RTCNT and RTCOR.
[Clearing conditions]
[Setting condition]
When RTCOR = RTCNT
Compare Match Interrupt Enable
Enables or disables interrupt requests (CMI) by
the CMF flag when the CMF flag is set to 1.
This bit is valid when refresh control is not
performed. When the refresh control is
performed, this bit is always cleared to 0 and
cannot be modified.
0: Interrupt request by CMF flag disabled
1: Interrupt request by CMF flag enabled
CAS-RAS Wait Control
These bits select the number of wait cycles to
be inserted between the CAS assert cycle and
RAS assert cycle in a DRAM/synchronous
DRAM refresh cycle.
00: Wait state not inserted
01: 1 wait state inserted
10: 2 wait states inserted
11: 3 wait states inserted
When 0 is written to CMF after reading CMF
= 1 while the RFSHE bit is cleared to 0
When CBR refreshing is executed while the
RFSHE bit is set to 1
Rev. 3.00 Mar 17, 2006 page 149 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300