D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 69

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Type
DMA controller
(DMAC)
EXDMA
controller
(EXDMAC)
16-bit timer
pulse unit
(TPU)
Symbol
TEND1
TEND0
(TEND1)
(TEND0)
DACK1
DACK0
(DACK1)
(DACK0)
EDREQ3
to
EDREQ0
ETEND3
to
ETEND0
EDACK3
to
EDACK0
EDRAK3
to
EDRAK0
TCLKA
TCLKB
TCLKC
TCLKD
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
FP-144G
(H8S/2678
Group)
82, 81,
40, 36
84, 83,
42, 41
141, 140,
35, 34
2, 142,
40, 36
4, 3, 42,
41
51, 50,
59, 58
45, 46,
49, 51
43, 44,
45, 46
48, 49
Pin No.
FP-144H
(H8S/2678R
Group)
82, 81,
40, 36
84, 83,
42, 41
141, 140,
35, 34
2, 142,
40, 36
4, 3, 42,
41
51, 50,
59, 58
45, 46,
49, 51
43, 44,
45, 46
48, 49
I/O
Output These signals indicate the end of
Output DMAC single address transfer
Input
Output These signals indicate the end of
Output EXDMAC single address transfer
Output These signals notify an external
Input
Input/
output
Input/
output
Rev. 3.00 Mar 17, 2006 page 17 of 926
Function
DMAC data transfer.
The input pins of TENDn and
(TENDn) are selected by the port
function control register 2 (PFCR2)
of port 3. (n = 1, 0)
acknowledge signals.
The input pins of DACKn and
(DACKn) are selected by the port
function control register 2 (PFCR2)
of port 3. (n = 1, 0)
These signals request EXDMAC
activation.
EXDMAC data transfer.
acknowledge signals.
device of acceptance and start of
execution of a DMA transfer
request.
External clock input pins.
TGRA_0 to TGRD_0 input capture
input/output compare output/PWM
output pins.
TGRA_1 and TGRB_1 input capture
input/output compare output/PWM
output pins.
Section 1 Overview
REJ09B0283-0300