D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 414
![MCU 3V 0K I-TEMP 144-QFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 414 of 981
- Download datasheet (6Mb)
Section 8 EXDMA Controller
accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The
address is fixed when SAT1 = 0, incremented when SAT1 = 1 and SAT0 = 0, and decremented
when SAT1 = 1 and SAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDSAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDSAR value to ensure that the correct value is output.
Do not write to EDSAR for a channel on which a transfer operation is in progress.
EXDMA Destination Address Register (EDDAR): When the EDDAR address is accessed as the
transfer destination, after the EDDAR value is output, EDDAR is updated with the address to be
accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The
address is fixed when DAT1 = 0, incremented when DAT1 = 1 and DAT0 = 0, and decremented
when DAT1 = 1 and DAT0 = 1.
The size of the increment or decrement is determined by the size of the data transferred. When the
DTSIZE bit in EDMDR = 0, the data is byte-size and the address is incremented or decremented
by 1; when DTSIZE = 1, the data is word-size and the address is incremented or decremented by
2.
When a repeat area setting is made, the operation conforms to that setting. The upper part of the
address set for the repeat area function is fixed, and is not affected by address updating.
When EDDAR is read during a transfer operation, a longword access must be used. During a
transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the
correct values may not be read if the upper and lower words are read separately. In a longword
access, the EXDMAC buffers the EDDAR value to ensure that the correct value is output.
Do not write to EDDAR for a channel on which a transfer operation is in progress.
Rev. 3.00 Mar 17, 2006 page 362 of 926
REJ09B0283-0300
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