D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 886

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 23 List of Registers
Register Name
DTC mode register A
DTC source address register
DTC mode register B
DTC destination address register
DTC transfer count register A
DTC transfer count register B
Serial expansion mode register *
EXDMA source address register_0
EXDMA destination address register_0 EDDAR_0
EXDMA transfer count register_0
EXDMA mode control register_0
EXDMA address control register_0
EXDMA source address register_1
EXDMA destination address register_1 EDDAR_1
EXDMA transfer count register_1
EXDMA mode control register_1
EXDMA address control register_1
EXDMA source address register_2
EXDMA destination address register_2 EDDAR_2
EXDMA transfer count register_2
EXDMA mode control register_2
EXDMA address control register_2
EXDMA source address register_3
EXDMA destination address register_3 EDDAR_3
EXDMA transfer count register 3
EXDMA mode control register 3
EXDMA address control register 3
Interrupt priority register A
Interrupt priority register B
Interrupt priority register C
Interrupt priority register D
Interrupt priority register E
Interrupt priority register F
Rev. 3.00 Mar 17, 2006 page 834 of 926
REJ09B0283-0300
1
Abbrevia-
tion
MRA
SAR
MRB
DAR
CRA
CRB
SEMR
EDSAR_0
EDTCR_0
EDMDR_0
EDACR_0
EDSAR_1
EDTCR_1
EDMDR_1
EDACR_1
EDSAR_2
EDTCR_2
EDMDR_2
EDACR_2
EDSAR_3
EDTCR_3
EDMDR_3
EDACR_3
IPRA
IPRB
IPRC
IPRD
IPRE
IPRF
Bit No.
8
24
8
24
16
18
8
32
32
32
16
16
32
32
32
16
16
32
32
32
16
16
32
32
32
16
16
16
16
16
16
16
16
Address
H'BC00 to DTC
H'BFFF
H'FDA8
H'FDC0
H'FDC4
H'FDC8
H'FDCC
H'FDCE
H'FDD0
H'FDD4
H'FDD8
H'FDDC
H'FDDE
H'FDE0
H'FDE4
H'FDE8
H'FDEC
H'FDEE
H'FDF0
H'FDF4
H'FDF8
H'FDFC
H'FDFE
H'FE00
H'FE02
H'FE04
H'FE06
H'FE08
H'FE0A
Module
DTC
DTC
DTC
DTC
DTC
SCI_2
EXDMAC_0 16
EXDMAC_0 16
EXDMAC_0 16
EXDMAC_0 16
EXDMAC_0 16
EXDMAC_1 16
EXDMAC_1 16
EXDMAC_1 16
EXDMAC_1 16
EXDMAC_1 16
EXDMAC_2 16
EXDMAC_2 16
EXDMAC_2 16
EXDMAC_2 16
EXDMAC_2 16
EXDMAC_3 16
EXDMAC_3 16
EXDMAC_3 16
EXDMAC_3 16
EXDMAC_3 16
INT
INT
INT
INT
INT
INT
Data
Width
16/32
16/32
16/32
16/32
16/32
16/32
8
16
16
16
16
16
16
2
2
2
2
2
Access
States
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2