D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 66

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 1 Overview
Type
Operating
mode control
System
control
Address bus
Data bus
Bus control
Rev. 3.00 Mar 17, 2006 page 14 of 926
REJ09B0283-0300
Symbol
DCTL
RES
STBY
BREQ
BREQO
BACK
FWE
A23 to
A0
D15 to
D0
CS7 to
CS0
AS
FP-144G
(H8S/2678
Group)
—
93
100
115
113
114
62
32 to 27,
25 to 20,
18 to 13,
11 to 6
72 to 75,
77 to 80,
63 to 66,
68 to 71
112, 111,
106 to 101
91
Pin No.
FP-144H
(H8S/2678R
Group)
132
93
100
115
113
114
—
32 to 27,
25 to 20,
18 to 13,
11 to 6
72 to 75,
77 to 80,
63 to 66,
68 to 71
112, 111,
106 to 101
91
I/O
Input
Input
Input
Input
Output External bus request signal used
Output Indicates that the bus has been
Input
Output These pins output an address.
Input/
output
Output Signals that select division areas 7
Output When this pin is low, it indicates that
Function
When this pin is driven high,
SDRAM dedicated to the
synchronous DRAM is output.
When not using the synchronous
DRAM interface, drive this pin low.
The level of this pin must not be
changed during operation.
When this pin is driven low, the chip
is reset.
When this pin is driven low, a
transition is made to hardware
standby mode.
Requests chip to release the bus to
an external bus master.
when an internal bus master
accesses external space when the
external bus is released.
released to an external bus master.
Enables/disables flash memory.
This pin is only used in the flash
memory version.
These pins constitute a bidirectional
data bus.
to 0 in the external address space.
address output on the address bus
is valid.