D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 162

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Section 5 Interrupt Controller
5.6.2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
Rev. 3.00 Mar 17, 2006 page 110 of 926
REJ09B0283-0300
interrupt request is sent to the interrupt controller.
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
execution of the current instruction has been completed.
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Interrupt Control Mode 2

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