D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 114
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 114 of 981
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Section 3 MCU Operating Modes
3.3.5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for any area by the bus controller, the bus mode switches to 8 bits.
In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.
3.3.6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.
In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.
3.3.7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the chip starts up in single-chip mode. External addresses cannot be used in single-chip mode.
The initial mode after a reset is single-chip mode, with all I/O ports available for use as
input/output ports. However, the mode can be switched to externally expanded mode by setting 1
to the EXPE bit of SYSCR and then the external address space is enabled. When externally
expanded mode is selected, all areas are initially designated as 16-bit access space. The function of
pins in ports A to H is the same as in externally expanded mode with on-chip ROM enabled.
In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.
Rev. 3.00 Mar 17, 2006 page 62 of 926
REJ09B0283-0300
Mode 5
Mode 6
Mode 7
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