D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 720

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 15 Serial Communication Interface (SCI, IrDA)
Bit
2
1
0
Smart Card Interface Mode (When SMIF in SCMR is 1)
Bit
7
6
5
Rev. 3.00 Mar 17, 2006 page 668 of 926
REJ09B0283-0300
Bit Name
MP
CKS1
CKS0
Bit Name
GM
BLK
PE
Initial Value
0
0
0
Initial Value
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
Clock Select 1 and 0:
These bits select the clock source for the on-chip
baud rate generator.
00:
01: /4 clock (n = 1)
10: /16 clock (n = 2)
11: /64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 15.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 15.3.9, Bit Rate
Register (BRR)).
Description
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of one bit), and clock
output control mode addition is performed. For
details, refer to section 15.7.8, Clock Output
Control.
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 15.7.3, Block Transfer Mode.
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. In Smart Card
interface mode, this bit must be set to 1.
clock (n = 0)