D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 9

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Item
All
6.2 Input/Output Pins
Table 6.1 Pin
Configuration
7.5.1 Transfer
Modes
Table 7.4 DMAC
Transfer Modes
Section 10 I/O Ports
Table 10.1 Port
Functions
Main Revisions in This Edition
Page
—
124
124
288
289
428 to
432
432
Revision (See Manual for Details)
All references to Hitachi, Hitachi, Ltd., Hitachi
Semiconductors, and other Hitachi brand names changed to
Renesas Technology Corp. Designation for categories
changed from “series” to “group”
Symbols amended
Upper column address strobe/upper data mask enable
(Before) UCAS/DQMU
Lower column address strobe/upper data mask enable
(Before) LCAS/DQML
I/O description amended
Data Transfer acknowledge 0 (DMAC) (Before) DACK0
(After) Output
Table 7.4 amended
Notes amended
Modes 3 *
CKE *
WE *
Notes: 1. Mode 3 is not supported in H8S/2378 Group.
2. These pins are not supported in H8S/2678 Group.
Transfer Mode
Short
address
mode
Transfer Mode
Full
address
mode
2
2
Dual address mode
(1) Sequential mode
• Memory address incremented or
• Number of transfers:
(2) Idle mode
• Memory address fixed
• Number of transfers:
(3) Repeat mode
• Memory address incremented or
• Continues transfer after sending
Normal mode
(1) Auto-request
• Transfer request is internally held
• Number of transfers (1 to 65,536) is
• Burst/cycle steal transfer can be
decremented by 1 or 2
1 to 65,536
1 to 65,536
decremented by 1 or 2
number of transfers (1 to 256) and
restoring the initial value
continuously sent
selected
DQML *
1
, 7
2
DQMU *
(After) LCAS/DQML
Rev. 3.00 Mar 17, 2006 page vii of l
(After) UCAS/DQMU
2
CAS *
Transfer Source
• TPU channel 0 to 5
• SCI transmission complete
• SCI reception complete
• A/D converter conversion
• External request
Transfer Source
Auto-request
compare match/input
capture A interrupt
interrupt
interrupt
end interrupt
2
RAS *
2
SDRAM *
Remarks
• Up to 4 channels can
• External request
• Single address mode
Remarks
• Max. 2-channel
operate independently
applies to channel B
only
applies to channel B
only
operation, combining
channels A and B
2