D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 284

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Section 6 Bus Controller (BSC)
6.9
6.9.1
When this LSI accesses external space, it can insert an idle cycle (T
following three cases: (1) when read accesses in different areas occur consecutively, (2) when a
write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs immediately
after a write cycle (in the H8S/2678R Group, it cannot insert an idle cycle in the condition (3)).
Insertion of a 1-state or 2-state idle cycle can be selected with the IDLC bit in BCR. By inserting
an idle cycle it is possible, for example, to avoid data collisions between ROM, etc., with a long
output floating time, and high-speed memory, I/O interfaces, and so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.65 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Rev. 3.00 Mar 17, 2006 page 232 of 926
REJ09B0283-0300
CS (area A)
CS (area B)
Address bus
Idle Cycle
Operation
Data bus
RD
(a) No idle cycle insertion
(ICIS1 = 0)
T
1
Bus cycle A
Long output floating time
Figure 6.65 Example of Idle Cycle Operation
T
2
(Consecutive Reads in Different Areas)
T
3
Bus cycle B
T
1
T
2
Data collision
Address bus
CS (area A)
CS (area B)
Data bus
RD
T
1
Bus cycle A
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
T
i
) between bus cycles in the
2
T
3
Idle cycle
T
Bus cycle B
i
T
1
T
2