D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 251

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Commands that are supported by this LSI are NOP, auto-refresh (REF), self-refresh (SELF), all
bank precharge (PALL), row address strobe bank-active (ACTV), read (READ), write (WRIT),
and mode-register write (MRS). Commands for bank control cannot be used.
6.7.2
With continuous synchronous DRAM space, the row address and column address are multiplexed.
In address multiplexing, the size of the shift of the row address is selected with bits MXC2 to
MXC0 in DRAMCR. The address-precharge-setting command (Prechrge-sel) can be output on the
upper column address. Table 6.8 shows the relation between the settings of MXC2 to MXC0 and
the shift size. The MXC2 bit should be set to 1 when the synchronous DRAM interface is used.
Table 6.8
Legend:
X: Don’t care
P: Precharge-sel
Row
address
Column
address
MXC2 MXC1 MXC0
Address Multiplexing
0
1
0
1
DRAMCR
Relation between Settings of Bits MXC2 to MXC0 and Address Multiplexing
x
0
1
x
0
1
0
1
0
1
0
1
0
1
x
x
10 bits A23 to
11 bits A23 to
8 bits A23 to
9 bits A23 to
Shift
Size
—
—
—
—
A23 to
A23 to
A23 to
A23 to
A23 to
A16
A16
A16
A16
A16
A16
A16
A16
A16
A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8
A15 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9
A15 A14 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10
A15 A14 A13 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11
P
P
P
P
P
P
P
P
P
P
P
P
Reserved (setting prohibited)
Reserved (setting prohibited)
P
P
P
P A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
P
P A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Rev. 3.00 Mar 17, 2006 page 199 of 926
P
P
Address Pins
A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
P
A8 A7 A6 A5 A4 A3 A2 A1 A0
Section 6 Bus Controller (BSC)
REJ09B0283-0300