D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 355

MCU 3V 0K I-TEMP 144-QFP

D12674RVFQ33D

Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet

Specifications of D12674RVFQ33D

Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
Set number of transfers
Set transfer source and
Normal mode setting
transfer destination
Read DMABCRL
Set DMABCRH
Set DMABCRL
Normal mode
Set DMACR
addresses
Figure 7.12 Example of Normal Mode Setting Procedure
[1]
[2]
[3]
[4]
[5]
[6]
[1] Set each bit in DMABCRH.
[2] Set the transfer source address in MARA, and
[3] Set the number of transfers in ETCRA.
[4] Set each bit in DMACRA and DMACRB.
[5] Read DTE = 0 and DTME = 0 in DMABCRL.
[6] Set each bit in DMABCRL.
• Set the FAE bit to 1 to select full address
• Specify enabling or disabling of internal
the transfer destination address in MARB.
• Set the transfer data size with the DTSZ bit.
• Specify whether MARA is to be incremented,
• Clear the BLKE bit to 0 to select normal
• Specify whether MARB is to be incremented,
• Select the activation source with bits DTF3 to
• Specify enabling or disabling of transfer end
• Set both the DTME bit and the DTE bit to 1 to
mode.
interrupt clearing with the DTA bit.
decremented, or fixed, with the SAID and
SAIDE bits.
mode.
decremented, or fixed, with the DAID and
DAIDE bits.
DTF0.
interrupts with the DTIE bit.
enable transfer.
Rev. 3.00 Mar 17, 2006 page 303 of 926
Section 7 DMA Controller (DMAC)
REJ09B0283-0300

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