D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 365

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Full Address Mode (Block Transfer Mode): Figure 7.21 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
A one-block transfer is performed for a single transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are executed by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle. Even if an NMI interrupt is generated
during data transfer, block transfer operation is not affected until data transfer for one block has
ended.
DREQ
DREQ
DREQ
DREQ Pin Falling Edge Activation Timing: Set the DTA bit in DMABCRH to 1 for the channel
for which the DREQ pin is selected.
Figure 7.22 shows an example of normal mode transfer activated by the DREQ pin falling edge.
Address bus
TEND
Figure 7.21 Example of Full Address Mode Transfer (Block Transfer Mode)
HWR
Bus release
LWR
RD
DMA
read
DMA
write
Block transfer
DMA
read
DMA
write
DMA
dead
Bus release
DMA
read
Rev. 3.00 Mar 17, 2006 page 313 of 926
DMA
Section 7 DMA Controller (DMAC)
write
Last block transfer
DMA
read
DMA
write
REJ09B0283-0300
DMA
dead
Bus
release