D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 197

• Manufacturer Part Number: D12674RVFQ33D
• Description: MCU 3V 0K I-TEMP 144-QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2600r

Specifications of D12674RVFQ33D

• Core Processor: H8S/2600
• Core Size: 16-Bit
• Speed: 33MHz
• Connectivity: IrDA, SCI
• Peripherals: DMA, POR, PWM, WDT
• Number Of I /o: 103
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Other names: HD6412674RVFQ33D; HD6412674RVFQ33D

Bit
7
6
5
4
3, 2
1
0
H8S/2678 Group
Bit Name
DRMI
—
TPC1
TPC0
—
RCD1
RCD0
Initial Value
0
0
0
0
All 0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Idle Cycle Insertion
An idle cycle can be inserted after a DRAM
read cycle when a continuous normal space
access cycle follows a DRAM read cycle. Idle
cycle insertion conditions, setting of number of
states, etc., comply with settings of bits ICIS1,
ICIS0, and IDLC in BCR register
0: Idle cycle not inserted
1: Idle cycle inserted
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
Precharge State Control
These bits select the number of states in the
RAS precharge cycle in normal access and
refreshing.
00: 1 state
01: 2 states
10: 3 states
11: 4 states
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
RAS-CAS Wait Control
These bits select a wait cycle to be inserted
between the RAS assert cycle and CAS assert
cycle.
00: Wait cycle not inserted
01: 1-state wait cycle inserted
10: 2-state wait cycle inserted
11: 3-state wait cycle inserted
Rev. 3.00 Mar 17, 2006 page 145 of 926
Section 6 Bus Controller (BSC)
REJ09B0283-0300