D12674RVFQ33D Renesas Electronics America, D12674RVFQ33D Datasheet - Page 375
![MCU 3V 0K I-TEMP 144-QFP](/photos/28/61/286116/144-lqfp__plqp0144kc-a_sml.jpg)
D12674RVFQ33D
Manufacturer Part Number
D12674RVFQ33D
Description
MCU 3V 0K I-TEMP 144-QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2600r
Datasheet
1.D12674RVFQ33V.pdf
(981 pages)
Specifications of D12674RVFQ33D
Core Processor
H8S/2600
Core Size
16-Bit
Speed
33MHz
Connectivity
IrDA, SCI
Peripherals
DMA, POR, PWM, WDT
Number Of I /o
103
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
HD6412674RVFQ33D
HD6412674RVFQ33D
HD6412674RVFQ33D
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
D12674RVFQ33DV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 375 of 981
- Download datasheet (6Mb)
Figure 7.31 shows an example of single address mode transfer activated by the DREQ pin low
level.
DREQ pin sampling is performed every cycle, with the rising edge of the next cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
Figure 7.31 Example of DREQ
Address bus
[1]
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] The DMAC cycle is started.
[4] [7] Acceptance is resumed after the single cycle is completed.
Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible.
DMA control
Channel
DREQ
DACK
Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of ,
and the request is held.
(As in [1], the DREQ pin low level is sampled on the rising edge of , and the request is held.)
Idle
[1]
Request
Bus release
Minimum of
DREQ Pin Low Level Activated Single Address Mode Transfer
DREQ
DREQ
2 cycles
[2]
[3]
Single
Request clear
Transfer source/
DMA single
destination
period
Acceptance resumes
Idle
[4]
Request
Rev. 3.00 Mar 17, 2006 page 323 of 926
Bus release
Minimum of
2 cycles
[5]
Section 7 DMA Controller (DMAC)
[6]
Single
Request clear
DMA single
Transfer source/
period
destination
Acceptance resumes
Idle
REJ09B0283-0300
[7]
release
Bus
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