HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet
HD64F3029XBL25V
Specifications of HD64F3029XBL25V
Related parts for HD64F3029XBL25V
HD64F3029XBL25V Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. H8/3029F-ZTAT 16 Hardware Manual Renesas 16-Bit Single-Chip ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used ...
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This LSI is a high performance single-chip microcontroller that integrates peripheral functions necessary for system configuration with an H8/300H CPU featuring a 32-bit internal architecture as its core. In addition, this LSI has an on-chip debugging function using the on-chip ...
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User's Manual on the H8/3029F-ZTAT Manual Title TM H8/3029F-ZTAT Hardware Manual H8/300H Series Programming Manual Usr's Manuals for development tools: Manual Title C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual H8S, H8/300 Series Simulator/Debugger User's Manual Renesas Technolgy Embedded Workshop ...
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Main Revisions for This Edition Item All 1.1 Overview Table 1.1 Features 12.2.4 Notes on Register Access Writing to RSTCSR Figure12.3 Format of Data Written to RSTCSR Page Revision (See Manual for Details) Product code changed HD64F3029X25 HD64F3029TE25 HD64F3029X25W HD64F3029TE25W ...
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Item 18.4.2 Programming/Erasing Interface Register (6) Flash Transfer Destination Address Register (FTDAR) 18.10.1 Serial Communication Interface Specification for Boot Mode • Inquiry and Selection States (2) Device Selection (11) New Bit-Rate Selection • Programming Figure18.27 Programming Sequence (3) 128-byte Programming ...
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Item 21.1 Electrical Characteristics of HD64F3029F25, HD64F3029TE25 21.1.2 DC Characteristics Table 21.2 DC Characteristics Page Revision (See Manual for Details) 713 Title amended 715, 716 Table and note amended Item Symbol Current Normal dissipation* operation Sleep mode ...
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Item 21.1.4 A/D Conversion Characteristics Table 21.8 A/D Conversion Characteristics 21.2 Electrical Characteristics of HD64F3029F25W and HD64F3029TE25W 21.2.2 DC Characteristics Table 21.12 DC Characteristics Rev. 2.0, 06/04, page vi of xxiv Page Revision (See Manual for Details) 725 Table amended ...
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Item 21.2.2 DC Characteristics Table 21.12 DC Characteristics 21.2.4 A/D Conversion Characteristics Table 21.18 A/D Conversion Characteristics 21.3 Electrical Characteristics of HD64F3029FBL25 and HD64F3029TEBL25 Page Revision (See Manual for Details) 731 Table and note amended Item Reference During A/D current ...
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Item 21.3.2 DC Characteristics Table 21.22 DC Characteristics 21.3.4 A/D Conversion Characteristics Table 21.28 A/D Conversion Characteristics Rev. 2.0, 06/04, page viii of xxiv Page Revision (See Manual for Details) 745, 746 Table and note amended Item Symbol Current Normal ...
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Item B.1 Addresses (EMC=1) B.2 Addresses (EMC=0) B.3 Functions FTDAR Flash Transfer Destination Address Register F.1 H8/3029F Product Code Lineup Page Revision (See Manual for Details) 807 Bit table amended Data Address Register Bus Bit 7 (Low) Name Width H'EE0B6 ...
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Rev. 2.0, 06/04, page x of xxiv ...
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Section 1 Overview............................................................................................1 1.1 Overview........................................................................................................................... 1 1.2 Block Diagram .................................................................................................................. 7 1.3 Pin Description.................................................................................................................. 8 1.3.1 Pin Arrangement .................................................................................................. 8 1.3.2 Pin Functions ....................................................................................................... 9 1.3.3 Pin Assignments in Each Mode ........................................................................... 14 Section 2 CPU....................................................................................................19 2.1 Overview........................................................................................................................... 19 2.1.1 ...
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Basic Operational Timing ................................................................................................. 55 2.9.1 Overview.............................................................................................................. 55 2.9.2 On-Chip Memory Access Timing........................................................................ 55 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 56 2.9.4 Access to External Address Space ....................................................................... 57 Section 3 MCU Operating Modes .....................................................................59 3.1 Overview........................................................................................................................... 59 ...
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Register Descriptions ........................................................................................................ 88 5.2.1 System Control Register (SYSCR) ...................................................................... 88 5.2.2 Interrupt Priority Registers A and B (IPRA, IPRB)............................................. 89 5.2.3 IRQ Status Register (ISR).................................................................................... 96 5.2.4 IRQ Enable Register (IER) .................................................................................. 97 5.2.5 IRQ Sense Control Register ...
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Address Output Method....................................................................................... 142 6.4 Basic Bus Interface ........................................................................................................... 144 6.4.1 Overview.............................................................................................................. 144 6.4.2 Data Size and Data Alignment............................................................................. 144 6.4.3 Valid Strobes....................................................................................................... 145 6.4.4 Memory Areas ..................................................................................................... 146 6.4.5 Basic Bus Control Signal Timing ........................................................................ 148 6.4.6 Wait ...
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Input/Output Pins................................................................................................. 200 7.1.5 Register Configuration......................................................................................... 200 7.2 Register Descriptions (1) (Short Address Mode) .............................................................. 202 7.2.1 Memory Address Registers (MAR) ..................................................................... 202 7.2.2 I/O Address Registers (IOAR) ............................................................................. 203 7.2.3 Execute Transfer Count Registers (ETCR).......................................................... 203 7.2.4 Data ...
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Register Descriptions ........................................................................................... 259 8.3 Port 2................................................................................................................................. 261 8.3.1 Overview.............................................................................................................. 261 8.3.2 Register Descriptions ........................................................................................... 262 8.4 Port 3................................................................................................................................. 265 8.4.1 Overview.............................................................................................................. 265 8.4.2 Register Descriptions ........................................................................................... 265 8.5 Port 4................................................................................................................................. 267 8.5.1 Overview.............................................................................................................. 267 8.5.2 Register Descriptions ........................................................................................... ...
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Timer Interrupt Status Register B (TISRB) ......................................................... 328 9.2.6 Timer Interrupt Status Register C (TISRC) ......................................................... 331 9.2.7 Timer Counters (16TCNT) .................................................................................. 333 9.2.8 General Registers (GRA, GRB) ........................................................................... 334 9.2.9 Timer Control Registers (16TCR) ....................................................................... 335 9.2.10 Timer ...
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Input Capture Setting ........................................................................................... 402 10.5 Interrupt ............................................................................................................................ 403 10.5.1 Interrupt Sources.................................................................................................. 403 10.5.2 A/D Converter Activation.................................................................................... 404 10.6 8-Bit Timer Application Example..................................................................................... 404 10.7 Usage Notes ...................................................................................................................... 405 10.7.1 Contention between 8TCNT Write and Clear...................................................... 405 10.7.2 Contention ...
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Note on Non-Overlapping Output ....................................................................... 439 Section 12 Watchdog Timer ..............................................................................441 12.1 Overview........................................................................................................................... 441 12.1.1 Features................................................................................................................ 441 12.1.2 Block Diagram ..................................................................................................... 442 12.1.3 Register Configuration......................................................................................... 442 12.2 Register Descriptions ........................................................................................................ 443 12.2.1 Timer Counter (TCNT)........................................................................................ 443 12.2.2 Timer Control/Status ...
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Section 14 Smart Card Interface........................................................................517 14.1 Overview........................................................................................................................... 517 14.1.1 Features................................................................................................................ 517 14.1.2 Block Diagram ..................................................................................................... 518 14.1.3 Pin Configuration................................................................................................. 518 14.1.4 Register Configuration......................................................................................... 519 14.2 Register Descriptions ........................................................................................................ 520 14.2.1 Smart Card Mode Register (SCMR) .................................................................... 520 14.2.2 Serial Status ...
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Input/Output Pins................................................................................................. 566 16.1.4 Register Configuration......................................................................................... 566 16.2 Register Descriptions ........................................................................................................ 567 16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 567 16.2.2 D/A Control Register (DACR)............................................................................. 567 16.2.3 D/A Standby Control Register (DASTCR).......................................................... 569 16.3 Operation .......................................................................................................................... 570 16.4 ...
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Usage Notes ......................................................................................................... 638 18.9 PROM Mode..................................................................................................................... 639 18.9.1 Pin Arrangement of the Socket Adapter .............................................................. 639 18.9.2 PROM Mode Operation ....................................................................................... 641 18.9.3 Memory-Read Mode............................................................................................ 642 18.9.4 Auto-Program Mode ............................................................................................ 643 18.9.5 Auto-Erase Mode................................................................................................. 643 18.9.6 Status-Read Mode................................................................................................ ...
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Note...................................................................................................................... 707 20.5 Hardware Standby Mode .................................................................................................. 708 20.5.1 Transition to Hardware Standby Mode................................................................ 708 20.5.2 Exit from Hardware Standby Mode..................................................................... 708 20.5.3 Timing for Hardware Standby Mode................................................................... 708 20.5.4 Timing for Hardware Standby Mode at Power-On.............................................. 709 20.6 ...
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Input Signal Timing ............................................................................................. 773 Appendix A Instruction Set ...............................................................................775 A.1 Instruction List .................................................................................................................. 775 A.2 Operation Code Maps ....................................................................................................... 790 A.3 Number of States Required for Execution ........................................................................ 793 Appendix B Internal I/O Registers ....................................................................802 B.1 Addresses (EMC ...
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Overview The H8/3029 is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture. The H8/3029 is a single-chip microcontroller (MCU) that integrates peripheral functions necessary for ...
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Notes on using the on-chip debugging functions incorporated in the H8/3029 The following must be noted when developing and debugging H8/3029 programs using the on- chip debugging function. 1. The on-chip emulator supports only the development and debugging of programs ...
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Table 1.1 Features Feature Description CPU Upward-compatible with the H8/300 CPU at the object-code level General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers, eight 16-bit registers, or eight 32-bit registers) High-speed operation Maximum clock rate: 25 ...
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Feature Description DMA controller Short address mode (DMAC) Maximum four channels available Selection of I/O mode, idle mode, or repeat mode Can be activated by compare match/input capture A interrupts from 16-bit timer channels conversion-end interrupts from ...
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Feature Description A/D converter Resolution: 10 bits Eight channels, with selection of single or scan mode Variable analog conversion voltage range Sample-and-hold function A/D conversion can be started by an external trigger or 8-bit timer compare- match DMAC can be ...
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Feature Description Product lineup Product Code Product (Catalog Product Type Code) H8/3029 HD64F3029F25 HD64F3029F25W HD64F3029FBL25 HD64F3029TE25 HD64F3029TE25W HD64F3029TEBL25 Rev. 2.0, 06/04, page 6 of 980 Regular product code Package (Internal Product (Renesas Code) Package Code) Classification HD64F3029F25 100-pin QFP (FP-100B) ...
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Block Diagram Figure 1.1 shows an internal block diagram EXTAL XTAL STBY RES FWE NMI /P6 7 LWR/P6 6 HWR/P6 5 RD/P6 4 AS/P6 3 BACK/P6 2 BREQ/P6 1 WAIT/ /P8 ...
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Pin Description 1.3.1 Pin Arrangement The pin arrangement of the H8/3029 FP-100B and TFP-100B packages is shown in figure 1. REF /P7 80 ...
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Pin Functions Table 1.2 summarizes the pin functions. Table 1.2 Pin Functions Pin No. FP-100B Type Symbol TFP-100B I/O Power V 35 11, 22, 44, SS 57, 65, 92 Internal step-down pin Clock ...
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Pin No. FP-100B Type Symbol TFP-100B I/O Operating mode MD 0 control RES System 63 control FWE 10 STBY 62 BREQ 59 BACK 60 Interrupts NMI 64 IRQ to 17, 16, 5 IRQ 90 ...
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Pin No. FP-100B Type Symbol TFP-100B I/O Data bus 23 Bus control HWR 71 LWR ...
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Pin No. FP-100B Type Symbol TFP-100B I/O 16-bit timer TCLKD TCLKA TIOCA to 99, 97 TIOCA 0 TIOCB to 100, 98, 2 TIOCB 96 0 8-bit timer TMO , TMO 2 ...
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Pin No. FP-100B Type Symbol TFP-100B I/O A/D and D/A converters REF I/O ports ...
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Pin Assignments in Each Mode Table 1.3 lists the pin assignments in each mode. Table 1.3 Pin Assignments in Each Mode (FP-100B or TFP-100B) Pin No. FP-100B TFP-100B Mode / ...
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Pin No. FP-100B TFP-100B Mode ...
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Pin No. FP-100B TFP-100B Mode /WAIT /BREQ /BACK STBY 62 RES 63 64 NMI 65 ...
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Pin No. FP-100B TFP-100B Mode /IRQ / 0 0 RFSH 88 P8 /IRQ / /IRQ / /IRQ / ADTRG 1 91 ...
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Overview The H8/300H CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 CPU. The H8/300H CPU has sixteen 16-bit general registers, can address a 16-Mbyte linear address space, and is ...
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High-speed operation All frequently-used instructions execute in two to four states Maximum clock frequency: 8/16/32-bit register-register add/subtract 8-bit register-register multiply: 16 ÷ 8-bit register-register divide: 16 16-bit register-register multiply: 32 ÷ 16-bit register-register divide: Two CPU operating ...
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CPU Operating Modes The H8/300H CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports Mbytes. CPU operating modes Note: * Cannot be selected in H8/3029 Normal ...
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Address Space Figure 2.2 shows a simple memory map for the H8/3029. The H8/300H CPU can address a linear address space with a maximum size of 64 kbytes in normal mode, and 16 Mbytes in advanced mode. For further ...
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Register Configuration 2.4.1 Overview The H8/300H CPU has the internal registers shown in figure 2.3. There are two types of registers: general registers and control registers. General Registers (ERn) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 Control ...
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General Registers The H8/300H CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used without distinction between data registers and address registers. When a general register is used as a data register, ...
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General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2.5 shows the stack. SP (ER7) 2.4.3 Control Registers The control registers are ...
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Bit 4—User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3—Negative Flag (N): Stores the value of the most significant bit of data, regarded as the sign bit. Bit ...
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Data Formats The H8/300H CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. ...
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General Data Type Register Data Format Word data Rn 15 Word data En MSB 31 Longword data ERn MSB Legend ERn: General register En: General register E Rn: General register R MSB: Most significant bit LSB: Least significant bit Figure ...
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Memory Data Formats Figure 2.8 shows the data formats on memory. The H8/300H CPU can access word data and longword data on memory, but word or longword data must begin at an even address attempt is made ...
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Instruction Set 2.6.1 Instruction Set Overview The H8/300H CPU has 62 types of instructions, which are classified in table 2.1. Table 2.1 Instruction Classification Function Instruction Data transfer MOV, PUSH* Arithmetic operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, ...
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Instructions and Addressing Modes Table 2.2 indicates the instructions available in the H8/300H CPU. Table 2.2 Instructions and Addressing Modes Function Instruction #xx Rn Data MOV BWL BWL transfer POP, PUSH — — MOVFPE, — — MOVTPE Arithmetic ADD, ...
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Tables of Instructions Classified by Function Tables 2.3 to 2.10 summarize the instructions in each functional category. The operation notation used in these tables is defined next. Operation Notation Rd General register (destination)* Rs General register (source)* Rn General ...
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Table 2.3 Data Transfer Instructions Instruction Size* Function MOV B/W/L (EAs) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B (EAs) Cannot be used in this ...
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Table 2.4 Arithmetic Operation Instructions Instruction Size* Function ADD,SUB B/W/L Rd ± Rs Performs addition or subtraction on data in two general registers immediate data and data in a general register. (Immediate byte data cannot be subtracted from ...
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Instruction Size* Function EXTS W/L Rd (sign extension) Extends byte data in the lower 8 bits of a 16-bit register to word data, or extends word data in the lower 16 bits of a 32-bit register to longword data, by ...
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Table 2.6 Shift Instructions Instruction Size* Function SHAL, B/W/L Rd (shift) SHAR Performs an arithmetic shift on general register contents. SHLL, B/W/L Rd (shift) SHLR Performs a logical shift on general register contents. ROTL, B/W/L Rd (rotate) ROTR Rotates general ...
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Table 2.7 Bit Manipulation Instructions Instruction Size* Function BSET B 1 (<bit-No.> of <EAd>) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower 3 ...
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Instruction Size* Function BLD B (<bit-No.> of <EAd>) Transfers a specified bit in a general register or memory operand to the carry flag. BILD B ¬ (<bit-No.> of <EAd>) Transfers the inverse of a specified bit in a general register ...
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Table 2.8 Branching Instructions Instruction Size Function Bcc — Branches to a specified address if address specified condition is met. The branching conditions are listed below. Mnemonic BRA (BT) BRN (BF) BHI BLS Bcc (BHS) BCS (BLO) BNE BEQ BVC ...
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Table 2.9 System Control Instructions Instruction Size* Function TRAPA — Starts trap-instruction exception handling RTE — Returns from an exception-handling routine SLEEP — Causes a transition to the power-down state LDC B/W (EAs) Moves the source operand contents to the ...
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Table 2.10 Block Transfer Instruction Instruction Size Function EEPMOV.B — if R4L repeat until else next; EEPMOV.W — then repeat until else next; Block transfer instruction. This instruction transfers the number of data bytes specified by R4L ...
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Operation field only Operation field and register fields op Operation field, register fields, and effective address extension op Operation field, effective address extension, and condition field op cc 2.6.5 Notes on Use of Bit Manipulation Instructions The BSET, BCLR, BNOT, ...
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Execution of BCLR Instruction BCLR #0, @P4DDR After Execution of BCLR Instruction Input/output Output Output DDR 1 1 Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since P4DDR is a write-only register, ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Modes The H8/300H CPU supports the eight addressing modes listed in table 2.11. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct ...
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Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @–ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) the lower 24 bits of which contain the address of a memory operand. After the ...
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Program-Counter Relative—@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction code is sign- extended to 24 bits and added to the 24-bit PC contents ...
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Processing States 2.8.1 Overview The H8/300H CPU has five processing states: the program execution state, exception-handling state, power-down state, reset state, and bus-released state. The power-down state includes sleep mode, software standby mode, and hardware standby mode. Figure 2.11 ...
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Program Execution State In this state the CPU executes program instructions in normal sequence. 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal program flow due to a reset, interrupt, ...
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End of bus release Bus-released state End of exception handling Exception-handling state RES = "High" *1 Reset state Notes: *1 From any state except hardware standby mode, a transition to the reset state occurs 4-5 whenever goes low. *2 From ...
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Exception-Handling Sequences Reset Exception Handling: Reset exception handling has the highest priority. The reset state is entered when the RES signal goes low. Reset exception handling starts after that, when RES changes from low to high. When reset exception ...
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Bus-Released State In this state the bus is released to a bus master other than the CPU, in response to a bus request. The bus masters other than the CPU are the DMA controller, the DRAM interface, and an ...
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Basic Operational Timing 2.9.1 Overview The H8/300H CPU operates according to the system clock (ø). The interval from one rise of the system clock to the next rise is referred “state.” A memory cycle or bus ...
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Address bus HWR LWR , , Figure 2.16 Pin States during On-Chip Memory Access 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in three states. The data bus ...
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Address bus HWR LWR , , Figure 2.18 Pin States during Access to On-Chip Supporting Modules 2.9.4 Access to External Address Space The external address space is divided into eight areas (areas ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection The H8/3029 has six operating modes (modes that are selected by the mode pins ( indicated in table 3.1. The input ...
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Mode externally expanded mode that enables access to external memory and peripheral devices and also enables access to the on-chip ROM. Mode 5 supports a maximum address space of 16 Mbytes. Mode 7 are single-chip modes that ...
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Mode Control Register (MDCR) MDCR is an 8-bit read-only register that indicates the current operating mode of the H8/3029. Bit 7 — Initial value 1 Read/Write — Reserved bits Note: * Determined by pins Bits ...
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System Control Register (SYSCR) SYSCR is an 8-bit register that controls the operation of the H8/3029. Bit 7 SSBY STS2 Initial value 0 Read/Write R/W R/W Standby timer select These bits select the waiting time at ...
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Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU and on-chip supporting modules wait for the internal clock oscillator to settle when software standby mode is exited by ...
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Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and to CS bus control signals (CS 0 outputs or fixed high, or placed in the high-impedance state in software standby mode. Bit 1 SSOE Description 0 In ...
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Mode 4 Ports and part of port A function as address pins A maximum 16-Mbyte address space. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. If all areas ...
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Pin Functions in Each Operating Mode The pin functions of ports and port 6 indicates their functions in each operating mode. Table 3.3 Pin Functions in Each Mode Port Mode 1 Mode 2 Port 1 ...
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Memory Map in Each Operating Mode Figures 3.1 and 3.2 show memory maps of the H8/3029. The address space is divided into eight areas. The EMC bit in BCR can be read and written to select either of the ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address H'7FFFF space H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O registers (1) H'EE0FF External ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'07FFFF H'080000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 Area 2 H'5FFFFF H'600000 External address Area 3 space H'7FFFFF H'800000 Area 4 H'9FFFFF ...
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Modes 1 and 2 (1-Mbyte expanded modes with on-chip ROM disabled) H'00000 Vector area H'000FF H'07FFF H'1FFFF H'20000 H'3FFFF H'40000 H'5FFFF H'60000 External address space H'7FFFF H'80000 H'9FFFF H'A0000 H'BFFFF H'C0000 H'DFFFF H'E0000 H'EE000 Internal I/O registers (1) H'EE0FF External ...
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Mode 5 (16-Mbyte expanded mode with on-chip ROM enabled) H'000000 Vector area H'0000FF On-chip ROM H'007FFF H'07FFFF H'080000 Area 0 H'1FFFFF H'200000 Area 1 H'3FFFFF H'400000 External address Area 2 space H'5FFFFF H'600000 Area 3 H'7FFFFF H'800000 Area 4 H'9FFFFF ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Exception Vector Table The exception sources are classified as shown in figure 4.1. Different vectors are assigned to different exception sources. Table 4.2 lists the exception sources and their vector addresses. Reset Exception Interrupts sources Trap instruction Rev. 2.0, ...
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Table 4.2 Exception Vector Table Exception Source Reset Reserved for system use External interrupt (NMI) Trap instruction (4 sources) External interrupt IRQ 0 External interrupt IRQ 1 External interrupt IRQ 2 External interrupt IRQ 3 External interrupt IRQ 4 External ...
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Reset 4.2.1 Overview A reset is the highest-priority exception. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of the ...
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Figure 4.2 Reset Sequence (Modes 1 and 3) Rev. 2.0, 06/04, page 77 of 980 ...
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RES Address bus RD HWR , LWR High (1), (3) Address of reset vector: (1) = H'000000, (3) = H'000002 (2), (4) Start address (contents of reset exception handling vector address) (5) Start address (6) ...
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Interrupts Interrupt exception handling can be requested by seven external sources (NMI, IRQ 36 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and indicates the number of interrupts of each type. The on-chip supporting ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. If the UE bit is set the system control register (SYSCR), the exception handling sequence sets the I bit CCR. ...
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Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. – – – – (ER7) Stack area Before exception ...
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Notes on Stack Usage When accessing word data or longword data, the H8/3029 regards the lowest address bit as 0. The stack should always be accessed by word access or longword access, and the value of the stack pointer ...
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SP TRAPA instruction executed SP set to H'FFFEFF Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: The diagram illustrates modes 3 and 4. Figure 4.6 Operation when SP Value is Odd CCR ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The interrupt controller has the following features: Interrupt priority registers (IPRs) for setting interrupt priorities Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis in interrupt ...
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Block Diagram Figure 5.1 shows a block diagram of the interrupt controller. ISCR NMI input IRQ input OVF TME . . . . . . . . . . TEI TEIE Interrupt controller Legend ISCR: IRQ sense control register ...
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Pin Configuration Table 5.1 lists the interrupt pins. Table 5.1 Interrupt Pins Name Nonmaskable interrupt External interrupt request Note: * NMI input is sometimes disabled when flash memory is being programmed or erased. For details see ...
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Register Descriptions 5.2.1 System Control Register (SYSCR) SYSCR is an 8-bit readable/writable register that controls software standby mode, selects the action of the UI bit in CCR, selects the NMI edge, and enables or disables the on-chip RAM. Only ...
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Bit 3—User Bit Enable (UE): Selects whether to use the UI bit in CCR as a user bit or an interrupt mask bit. Bit 3 UE Description 0 UI bit in CCR is used as interrupt mask bit 1 UI ...
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Interrupt Priority Register A (IPRA): IPRA is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRA7 IPRA6 Initial value 0 Read/Write R/W R/W Priority level A6 Selects the priority level of IRQ interrupt requests ...
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Bit 7—Priority Level A7 (IPRA7): Selects the priority level of IRQ Bit 7 IPRA7 Description 0 IRQ interrupt requests have priority level 0 (low priority IRQ interrupt requests have priority level 1 (high priority) 0 Bit 6—Priority Level ...
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Bit 3—Priority Level A3 (IPRA3): Selects the priority level of WDT, DRAM interface, and A/D converter interrupt requests. Bit 3 IPRA3 Description 0 WDT, DRAM interface, and A/D converter interrupt requests have priority level 0 (low priority) 1 WDT, DRAM ...
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Interrupt Priority Register B (IPRB): IPRB is an 8-bit readable/writable register in which interrupt priority levels can be set. Bit 7 IPRB7 IPRB6 Initial value 0 Read/Write R/W R/W Priority level B6 Selects the priority level of 8-bit timer channel ...
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Bit 7—Priority Level B7 (IPRB7): Selects the priority level of 8-bit timer channel 0, 1 interrupt requests. Bit 7 IPRB7 Description 0 8-bit timer channel 0, 1 interrupt requests have priority level 0 (low priority)(Initial value) 1 8-bit timer channel ...
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Bit 3—Priority Level B3 (IPRB3): Selects the priority level of SCI channel 0 interrupt requests. Bit 3 IPRB3 Description 0 SCI channel 0 interrupt requests have priority level 0 (low priority) 1 SCI channel 0 interrupt requests have priority level ...
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IRQ Status Register (ISR) ISR is an 8-bit readable/writable register that indicates the status of IRQ requests. Bit 7 — Initial value 0 Read/Write — Reserved bits Note: Only 0 can be written, to clear flags. * ISR is ...
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IRQ Enable Register (IER) IER is an 8-bit readable/writable register that enables or disables IRQ Bit 7 — Initial value 0 Read/Write R/W R/W Reserved bits IER is initialized to H' reset and in hardware standby mode. ...
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IRQ Sense Control Register (ISCR) ISCR is an 8-bit readable/writable register that selects level sensing or falling-edge sensing of the inputs at pins IRQ to IRQ . 5 0 Bit 7 — Initial value 0 Read/Write R/W Reserved bits ...
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Interrupt Sources The interrupt sources include external interrupts (NMI, IRQ 5.3.1 External Interrupts There are seven external interrupts: NMI and IRQ can be used to exit software standby mode. NMI: NMI is the highest-priority interrupt and is always accepted, ...
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Figure 5.3 shows the timing of the setting of the interrupt flags (IRQnF). IRQn input pin IRQnF Note Figure 5.3 Timing of Setting of IRQnF Interrupts IRQ to IRQ have vector numbers 12 to 17. ...
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Table 5.3 Interrupt Sources, Vector Addresses, and Priority Interrupt Source Origin NMI External pins IRQ 0 IRQ 1 IRQ 2 IRQ 3 IRQ 4 IRQ 5 Reserved — WOVI Watchdog (interval timer) timer CMI DRAM (compare match) interface Reserved — ...
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Interrupt Source Origin IMIA2 16-bit timer (compare match/ channel 2 input capture A2) IMIB2 (compare match/ input capture B2) OVI2 (overflow 2) Reserved — CMIA0 8-bit timer (compare match channel 0/1 A0) CMIB0 (compare match B0) CMIA1/CMIB1 (compare match A1/B1) ...
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Interrupt Source Origin ERI0 SCI (receive error 0) channel 0 RXI0 (receive data full 0) TXI0 (transmit data empty 0) TEI0 (transmit end 0) ERI1 SCI (receive error 1) channel 1 RXI1 (receive data full 1) TXI1 (transmit data empty ...
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Interrupt Operation 5.4.1 Interrupt Handling Process The H8/3029 handles interrupts differently depending on the setting of the UE bit. When interrupts are controlled by the I bit. When interrupts are controlled by the ...
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Program execution state Interrupt requested? Yes Priority level 1? Yes No IRQ 0 Yes No IRQ 1 Yes TEI2 Yes Save PC and CCR Read vector address Branch to interrupt service routine Figure 5.4 Process Up to Interrupt Acceptance when ...
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If an interrupt condition occurs and the corresponding interrupt enable bit is set interrupt request is sent to the interrupt controller. When the interrupt controller receives one or more interrupt requests, it selects the highest- priority request, ...
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Figure 5.5 shows the transitions among the above states. a. All interrupts are unmasked I 0 Figure 5.5 Interrupt Masking State Transitions (Example) Figure 5 flowchart showing how interrupts are accepted when interrupt ...
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Priority level 1? No IRQ 0 Yes IRQ Figure 5.6 Process Up to Interrupt Acceptance when Rev. 2.0, 06/04, page 108 of 980 Program execution state Interrupt requested? Yes Yes NMI No No Yes ...
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Interrupt Sequence Figure 5.7 shows the interrupt sequence in mode 2 when the program code and stack are in an external memory area accessed in two states via a 16-bit bus. Figure 5.7 Interrupt Sequence Rev. 2.0, 06/04, page ...
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Interrupt Response Time Table 5.5 indicates the interrupt response time from the occurrence of an interrupt request until the first instruction of the interrupt service routine is executed. Table 5.5 Interrupt Response Time No. Item 1 Interrupt priority decision ...
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Usage Notes 5.5.1 Contention between Interrupt and Interrupt-Disabling Instruction When an instruction clears an interrupt enable bit disable the interrupt, the interrupt is not disabled until after execution of the instruction is completed interrupt ...
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Instructions that Inhibit Interrupts The LDC, ANDC, ORC, and XORC instructions inhibit interrupts. When an interrupt occurs, after determining the interrupt priority, the interrupt controller requests a CPU interrupt. If the CPU is currently executing one of these interrupt-inhibiting ...
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Section 6 Bus Controller 6.1 Overview The H8/3029 has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently ...
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Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle Bus arbitration ...
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Block Diagram Figure 6.1 shows a block diagram of the bus controller. Area Internal address bus decoder Internal signals CPU bus request signal DMAC bus request signal DRAM interface bus request signal CPU bus acknowledge signal DMAC bus acknowledge ...
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Pin Configuration Table 6.1 summarizes the input/output pins of the bus controller. Table 6.1 Bus Controller Pins Name Abbreviation Chip select Address strobe RD Read HWR High write LWR Low write ...
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Register Configuration Table 6.2 summarizes the bus controller's registers. Table 6.2 Bus Controller Registers 1 Address* Name H'EE020 Bus width control register H'EE021 Access state control register H'EE022 Wait control register H H'EE023 Wait control register L H'EE013 Bus ...
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Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area. Bit 7 ABW7 Modes Initial value and 7 Read/Write R/W Modes Initial ...
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Access State Control Register (ASTCR) ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two states or three states Bit AST7 AST6 Initial value 1 1 Read/Write R/W R/W Bits selecting number ...
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WCRH 7 6 Bit W71 W70 Initial value 1 1 Read/Write R/W R/W Bits 7 and 6—Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space ...
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Bit 3 Bit 2 W51 W50 Description 0 0 Program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed program wait states inserted ...
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Bits 5 and 4—Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit ...
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Bus Release Control Register (BRCR) BRCR is an 8-bit readable/writable register that enables address output on bus lines A enables or disables release of the bus to an external device. Bit 7 A23E Modes Initial value ...
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Bit 5—Address 21 Enable (A21E): Enables PA Writing 0 in this bit enables A be modified and PA has its ordinary port functions. 6 Bit 5 A21E Description the input/output pin ...
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Bit 7—Idle Cycle Insertion 1 (ICIS1): Selects whether one idle cycle state inserted between bus cycles in case of consecutive external read cycles for different areas. Bit 7 ICIS1 Description 0 No idle cycle inserted in case ...
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Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access (burst access on match of address bits ...
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When EMC is cleared to 0, addresses of some internal I/O registers are moved. For details, refer to appendix B.2, Addresses (EMC = 0). When the RDEA bit is 0, EMC must not be cleared to 0. Bit 1—Area Division ...
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Chip Select Control Register (CSCR) CSCR is an 8-bit readable/writable register that enables or disables output of chip select signals output of a chip select signal is enabled by a setting in ...
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DRAM Control Register A (DRCRA Bit DRAS2 DRAS1 Initial value 0 0 Read/Write R/W R/W DRCRA is an 8-bit readable/writable register that selects the areas that have a DRAM interface function, and the access mode, and enables ...
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When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than 000 must not be performed. Bit 4—Reserved: This bit cannot be modified and is always read as 1. Bit 3—Burst Access ...
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Bit 0—Refresh Pin Enable (RFSHE): Enables or disables RFSH pin refresh signal output. If areas are not designated as DRAM space, this bit should not be set to 1. Bit 0 RFSHE Description RFSH pin refresh signal ...
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Bit 7 Bit 6 MXC1 MXC0 Description 0 0 Column address: 8 bits Compared address: Modes 1, 2 Modes Column address: 9 bits Compared address: Modes 1, 2 Modes Column address: ...
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Bit 3—Reserved: This bit cannot be modified and is always read as 1. Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (T be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of ...
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Note: * Only 0 can be written to clear the flag. Bit 7—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. Bit 7 CMF Description 0 [Clearing conditions] When the chip is ...
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Refresh Timer Counter (RTCNT Bit Initial value 0 0 Read/Write R/W R/W RTCNT is an 8-bit readable/writable up-counter. RTCNT is incremented by an internal clock selected by bits CKS2 to CKS0 in RTMCSR. When RTCNT matches RTCOR ...
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Address Control Register (ADRCR) ADRCR is an 8-bit readable/writable register that selects either address update mode 1 or address update mode 2 as the address output method. Bit 7 6 — — Initial value 1 1 R/W — — ...
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Operation 6.3.1 Area Division The external address space is divided into areas Each area has a size of 128 kbytes in the 1-Mbyte modes, or 2-Mbytes in the 16-Mbyte modes. Figure 6.2 shows a general view ...
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H'000000 H'1FFFFF H'200000 H'3FFFFF H'400000 H'5FFFFF H'600000 H'7FFFFF H'800000 H'9FFFFF H'A00000 H'BFFFFF H'C00000 H'DFFFFF H'E00000 H'FEE000 On-chip registers (1) H'FEE0FF H'FEE100 H'FF7FFF H'FF8000 H'FF8FFF H'FF9000 H'FFEF1F H'FFEF20 H'FFFEFF H'FFFF00 H'FFFF1F H'FFFF20 On-chip registers (2) H'FFFFE9 H'FFFFEA H'FFFFFF (A) Memory map ...
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Bus Specifications The external space bus specifications consist of three elements: (1) bus width, (2) number of access states, and (3) number of program wait states. The bus width and number of access states for on-chip memory and registers ...
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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH/WCRL ABWn ASTn Wn1 0 0 — — Note 6.3.3 Memory Interfaces The H8/3029 memory ...
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Chip Select Signals For each of areas the H8/3029 can output a chip select signal (CS when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of a CSn signal. Output ...
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Address Output Method The H8/3029 provides a choice of two address update methods: either the same method as in the previous H8/300H Series (address update mode 1 method in which address update is restricted to external space ...
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Cautions: When using address update modes, the following points should be noted. When address update mode 2 is selected, the address in an internal space (on-chip memory or internal I/O) access cycle is not output externally. In order to secure ...
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Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data Size and Data Alignment ...
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In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd ...
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Table 6.4 Data Buses Used and Valid Strobes Access Area Size Read/Write 8-bit Byte Read access Write area 16-bit Byte Read access area Write Word Read Write Notes: 1. Undetermined data means that unpredictable data is output. 2. Invalid means ...
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Areas external expansion mode, areas are entirely external space. When area external space is accessed, signals CS Basic bus interface or DRAM interface can be selected for areas 2 to ...
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Basic Bus Control Signal Timing 8-Bit, Three-State-Access Areas Figure 6.9 shows the timing of bus control signals for an 8-bit, three-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait ...
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Two-State-Access Areas Figure 6.10 shows the timing of bus control signals for an 8-bit, two-state-access area. The upper ) is used in accesses to these areas. The LWR pin is always high. Wait states data bus ( ...
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Three-State-Access Areas Figures 6.11 to 6.13 show the timing of bus control signals for a 16-bit, three-state-access area. In these areas, the upper data bus (D bus ( accesses to odd addresses. Wait states can ...
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Address bus Read access HWR LWR Write access Note Figure 6.12 ...
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Address bus Read access HWR LWR Write access Note Figure 6.13 Bus Control Signal Timing ...
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Two-State-Access Areas: Figures 6.14 to 6.16 show the timing of bus control signals for a 16-bit, two-state-access area. In these areas, the upper data bus (D even addresses and the lower data bus (D be inserted. Address bus Read ...
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Address bus Read access Write access Note Figure 6.15 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (2) Rev. 2.0, 06/04, page 154 of 980 Bus cycle T 1 Odd external address in area n ...
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Address bus Read access Write access Note Figure 6.16 Bus Control Signal Timing for 16-Bit, Two-State-Access Area (3) 6.4.6 Wait Control When accessing external space, the H8/3029 can extend the bus cycle by inserting one ...
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This is useful when inserting four or more T different external devices. The WAITE bit setting applies to all areas. Pin waits cannot be inserted in DRAM space. Figure 6.17 shows an example of the timing for insertion of one ...
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DRAM Interface 6.5.1 Overview The H8/3029 is provided with a DRAM interface with functions for DRAM control signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of DRAM. In the expanded modes, external address space ...
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Table 6.5 Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space (RAS Output Pin) DRAS2 DRAS1 DRAS0 Area Normal space 1 Normal space 1 0 Normal space 1 Normal space Normal space ...
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Table 6.6 Settings of Bits MXC1 and MXC0 and Address Multiplexing Method Column DRCRB Address MXC1 MXC0 Bits Row bits address 1 9 bits bits 1 Illegal setting Column — — — address Note: ...
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Table 6.7 DRAM Interface Pins With DRAM Pin Designated Name UCAS PB4 Upper column address strobe LCAS PB5 Lower column address strobe HWR UCAS Upper column address strobe LWR LCAS Lower column address strobe CS RAS Row address 2 2 ...
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/ Read access ( ) / Write access ( ) Note ...
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/ Read access ( ) / Write access ( ) Note: ...
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The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin /PB ...
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When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0, PB5 can be used as an input/output ...
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Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number ...
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Table 6.9 Correspondence between Settings of MXC1 and MXC0 Bits and ABWCR, and Row Address Compared in Burst Access DRCRB Operating Mode MXC1 Modes 1 and 2 0 (1-Mbyte) 1 Modes 3, 4, and 5 0 (16-Mbyte) 1 Note: n ...
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DRAM access / Note Figure 6.23 Example of Operation Timing in RAS Down Mode ...
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Note Figure 6.24 RAS RAS RAS RASn Negation Timing when RAS Down Mode is Selected Rev. 2.0, 06/04, page 168 of 980 DRAM access cycle (a) Access to DRAM space with ...
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When RAS down mode is selected, the CAS-before-RAS refresh function provided with this DRAM interface must always be used as the DRAM refreshing method. When a refresh operation is performed, the RAS signal goes high immediately beforehand. The refresh interval ...
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Refresh Control The H8/3029 is provided with a CAS-before-RAS (CBR) function and self-refresh function as DRAM refresh control functions. CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit DRCRB. With CBR refreshing, RTCNT counts ...
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RTCNT RTCOR Refresh request signal and CMF bit setting signal Address bus / Note address update mode 1, the area 2 start address is output. In address update mode 2, ...