HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 907

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

TISRB—Timer Interrupt Status Register B
Rev. 2.0, 06/04, page 878 of 980
Input capture/compare match interrupt enable B2
Note : * Only 0 can be written, to clear the flag.
0
1
Input capture/compare match interrupt enable B1
IMIB2 interrupt requested by IMFB2 flag is disabled
IMIB2 interrupt requested by IMFB2 flag is enabled
0
1
Input capture/compare match interrupt enable B0
0
1
IMIB1 interrupt requested by IMFB1 flag is disabled
IMIB1 interrupt requested by IMFB1 flag is enabled
Bit:
Initial value:
Read/Write:
Input capture/compare match flag B2
IMIB0 interrupt requested by IMFB0 flag is disabled
IMIB0 interrupt requested by IMFB0 flag is enabled
0
1
Input capture/compare match flag B1
[Clearing condition]
Read IMFB2 when IMFB2=1, then write 0 in IMFB2.
[Setting conditions]
TCNT2=GRB2 when GRB2 functions as an output compare register.
TCNT2 value is transferred to GRB2 by an input capture signal when GRB2
functions as an input capture register.
0
1
Input capture/compare match flag B0
0
1
[Clearing condition]
Read IMFB1 when IMFB1=1, then write 0 in IMFB1.
[Setting conditions]
TCNT1=GRB1 when GRB1 functions as an output compare register.
TCNT1 value is transferred to GRB1 by an input capture signal when GRB1
functions as an input capture register.
—
—
7
1
[Clearing condition]
Read IMFB0 when IMFB0=1, then write 0 in IMFB0.
[Setting conditions]
TCNT0=GRB0 when GRB0 functions as an output compare register.
TCNT0 value is transferred to GRB0 by an input capture signal when GRB0
functions as an input capture register.
IMIEB2
R/W
6
0
IMIEB1
R/W
5
0
IMIEB0
R/W
4
0
H'FFF65
—
—
3
1
IMFB2
R/(W)*
(Initial value)
2
0
(Initial value)
IMFB1
R/(W)*
1
0
(Initial value)
16-bit timer (all channels)
R/(W)*
IMFB0
(Initial value)
0
0
(Initial value)
(Initial value)