HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 729

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Bit 7—Software Standby (SSBY): Enables transition to software standby mode. When software
standby mode is exited by an external interrupt, this bit remains set to 1 after the return to normal
operation. To clear this bit, write 0.
Bit 7
SSBY
0
1
Bits 6 to 4—Standby Timer Select (STS2 to STS0): These bits select the length of time the CPU
and on-chip supporting modules wait for the clock to settle when software standby mode is exited
by an external interrupt. If the clock is generated by a crystal resonator, set these bits according to
the clock frequency so that the waiting time will be at least 7 ms (oscillation settling time). See
table 20.3. If an external clock is used, set these bits so that the waiting time will be at least
100 µs.
Bit 6
STS2
0
1
Bit 1—Software Standby Output Port Enable (SSOE): Specifies whether the address bus and
bus control signals (CS
outputs or fixed high, or placed in the high-impedance state in software standby mode.
Bit 1
SSOE
0
1
Rev. 2.0, 06/04, page 700 of 980
Bit 5
STS1
0
1
0
1
Description
SLEEP instruction causes transition to sleep mode
SLEEP instruction causes transition to software standby mode
Description
In software standby mode, the address bus and bus control signals
are all high-impedance
In software standby mode, the address bus retains its output state
and bus control signals are fixed high
Bit 4
STS0
0
1
0
1
0
1
0
1
0
to CS
7
, AS, RD, HWR, LWR, UCAS, LCAS, and RFSH) are kept as
Description
Waiting time = 8,192 states
Waiting time = 16,384 states
Waiting time = 32,768 states
Waiting time = 65,536 states
Waiting time = 131,072 states
Waiting time = 262,144 states
Waiting time = 1,024 states
Illegal setting
(Initial value)
(Initial value)
(Initial value)

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