HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 26

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.2 Register Descriptions ........................................................................................................ 567
16.3 Operation .......................................................................................................................... 570
16.4 D/A Output Control .......................................................................................................... 571
Section 17 RAM ................................................................................................573
17.1 Overview........................................................................................................................... 573
17.2 System Control Register (SYSCR) ................................................................................... 574
17.3 Operation .......................................................................................................................... 575
Section 18 ROM ................................................................................................577
18.1 Features ............................................................................................................................. 577
18.2 Overview........................................................................................................................... 579
18.3 Pin Configuration.............................................................................................................. 587
18.4 Register Configuration...................................................................................................... 588
18.5 On-Board Programming Mode ......................................................................................... 612
18.6 Protection .......................................................................................................................... 630
18.7 Flash Memory Emulation in RAM ................................................................................... 634
18.8 Switching between User MAT and User Boot MAT ........................................................ 637
16.1.3 Input/Output Pins................................................................................................. 566
16.1.4 Register Configuration......................................................................................... 566
16.2.1 D/A Data Registers 0 and 1 (DADR0/1).............................................................. 567
16.2.2 D/A Control Register (DACR)............................................................................. 567
16.2.3 D/A Standby Control Register (DASTCR).......................................................... 569
17.1.1 Block Diagram ..................................................................................................... 573
17.1.2 Register Configuration......................................................................................... 574
18.2.1 Block Diagram ..................................................................................................... 579
18.2.2 Operating Mode ................................................................................................... 580
18.2.3 Mode Comparison................................................................................................ 581
18.2.4 Flash MAT Configuration.................................................................................... 583
18.2.5 Block Division ..................................................................................................... 583
18.2.6 Programming/Erasing Interface ........................................................................... 584
18.4.1 Registers............................................................................................................... 588
18.4.2 Programming/Erasing Interface Register............................................................. 591
18.4.3 Programming/Erasing Interface Parameter .......................................................... 597
18.4.4 RAM Control Register (RAMCR) ....................................................................... 608
18.4.5 Flash Vector Address Control Register (FVACR)............................................... 609
18.4.6 Flash Vector Address Data Register (FVADR) ................................................... 611
18.5.1 Boot Mode ........................................................................................................... 612
18.5.2 User Program Mode............................................................................................. 615
18.5.3 User Boot Mode................................................................................................... 626
18.6.1 Hardware Protection ............................................................................................ 630
18.6.2 Software Protection.............................................................................................. 631
18.6.3 Error Protection.................................................................................................... 632
Rev. 2.0, 06/04, page xxi of xxiv