HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 360

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.2.6
TISRC is an 8-bit readable/writable register that indicates 16TCNT overflow or underflow and
enables or disables overflow interrupt requests.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by
the OVF2 when OVF2 flag is set to 1.
Bit 6
OVIE2
0
1
Bit 5—Overflow Interrupt Enable 1 (OVIE1): Enables or disables the interrupt requested by
the OVF1 when OVF1 flag is set to 1.
Bit 5
OVIE1
0
1
Initial value
Read/Write
Note: * Only 0 can be written, to clear the flag.
Timer Interrupt Status Register C (TISRC)
Description
OVI2 interrupt requested by OVF2 flag is disabled
OVI2 interrupt requested by OVF2 flag is enabled
Description
OVI1 interrupt requested by OVF1 flag is disabled
OVI1 interrupt requested by OVF1 flag is enabled
Bit
Reserved bit
—
—
7
1
OVIE2
R/W
6
0
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
OVIE1
R/W
5
0
OVIE0
R/W
4
0
Reserved bit
—
—
3
1
R/(W)*
OVF2
Rev. 2.0, 06/04, page 331 of 980
Overflow flags 2 to 0
Status flags indicating
interrupts by OVF flags
2
0
R/(W)*
OVF1
1
0
R/(W)*
OVF0
(Initial value)
(Initial value)
0
0