HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 449

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
11.2.3
PBDDR is an 8-bit write-only register that selects input or output for each pin in port B.
Port B is multiplexed with pins TP
be set to 1. For further information about PBDDR, see section 8.12, Port B.
11.2.4
PBDR is an 8-bit readable/writable register that stores TPC output data for groups 2 and 3, when
these TPC output groups are used.
For further information about PBDR, see section 8.12, Port B.
Rev. 2.0, 06/04, page 420 of 980
Bit
Initial value
Read/Write
Note: * Bits selected for TPC output by NDERB settings become read-only bits.
Bit
Initial value
Read/Write
Port B Data Direction Register (PBDDR)
Port B Data Register (PBDR)
PB
R/(W)*
PB
7
DDR
W
0
7
0
7
7
PB
R/(W)*
6
PB
DDR
6
0
W
0
6
6
15
PB
to TP
R/(W)*
5
PB
DDR
5
0
W
0
5
8
. Bits corresponding to pins used for TPC output must
5
Port B direction 7 to 0
These bits select input or
output for port B pins
Port B data 7 to 0
These bits store output data
for TPC output groups 2 and 3
PB
R/(W)*
4
PB
DDR
4
0
W
0
4
4
PB
R/(W)*
3
PB
DDR
W
3
0
0
3
3
PB
R/(W)*
2
PB
DDR
W
0
2
0
2
2
PB
R/(W)*
1
PB
DDR
W
0
1
1
0
1
PB
R/(W)*
0
PB
DDR
W
0
0
0
0
0

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