HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 430

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Compare Match Count Mode
Caution
Do not set 16-bit counter mode and compare match count mode simultaneously within the same
group, as the 8TCNT input clock will not be generated and the counters will not operate.
Channels 0 and 1:
When bits CKS2 to CKS0 are set to (100) in 8TCR1, 8TCNT1 counts channel 0 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Note: When bit ICE = 1 in 8TCSR1, the compare match register function of TCORB0 in
Channels 2 and 3:
When bits CKS2 to CKS0 are set to (100) in 8TCR3, 8TCNT3 counts channel 2 compare
match A events.
CMF flag setting, interrupt generation, TMO pin output, counter clearing, and so on, is in
accordance with the settings for each channel.
Setting when Input Capture Occurs
Counter Clear Specification
OVF Flag Operation
The CMFB flag is set to 1 in 8TCSR2 and 8TCSR3 when the ICE bit is 1 in TCSR3
and input capture occurs.
TMIO3 pin input capture input signal edge detection is selected by bits OIS3 and OIS2
in 8TCSR2.
If counter clear on compare match has been selected by the CCLR1 and CCLR0 bits in
8TCR2, the 16-bit counter (both 8TCNT2 and 8TCNT3) is cleared.
The settings of the CCLR1 and CCLR0 bits in 8TCR3 are ignored. The lower 8 bits
cannot be cleared independently.
The OVF flag is set to 1 in 8TCSR2 when the 16-bit counter (8TCNT2 and 8TCNT3)
overflows (from H'FFFF to H'0000).
The OVF flag is set to 1 in 8TCSR3 when the 8-bit counter (8TCNT3) overflows (from
H'FF to H'00).
channel 0 cannot be used.
Rev. 2.0, 06/04, page 401 of 980