HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 538
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Note: When switching from transmitting or receiving to simultaneous transmitting and receiving, clear both the TE bit
Transmitting and Receiving Data Simultaneously (Synchronous Mode): Figure 13.20 shows a
sample flowchart for transmitting and receiving serial data simultaneously and indicates the
procedure to follow.
Figure 13.20 Sample Flowchart for Simultaneous Serial Transmitting and Receiving
No
No
No
Clear TE and RE bits to 0 in SCR
Read receive data from RDR, and
Start of transmitting and receiving
and the RE bit to 0, then set both bits to 1 simultaneously.
Write transmit data in TDR and
clear TDRE flag to 0 in SSR
clear RDRF flag to 0 in SSR
Read ORER flag in SSR
Read RDRF flag in SSR
Read TDRE flag in SSR
End of transmitting
and receiving?
ORER = 1
TDRE = 1
RDRF = 1
Initialize
<End>
Yes
No
Yes
Yes
Error handling
Yes
(4)
(5)
(1)
(2)
(3)
(1)
(2)
(3)
(4)
(5)
SCI initialization: the transmit data output function of the
TxD pin and the read data input function of the RxD pin
are selected, enabling simultaneous transmitting and
receiving.
SCI status check and transmit data write: read SSR, check
that the TDRE flag is 1, then write transmit data in TDR
and clear the TDRE flag to 0.
can also be given by the TXI interrupt.
Receive error handling: if a receive error occurs, read the
ORER flag in SSR, then after executing the necessary
error handling, clear the ORER flag to 0.
ORER flag remains set to 1.
SCI status check and receive data read: read SSR, check
that the RDRF flag is 1, then read receive data from RDR
and clear the RDRF flag to 0. Notification that the RDRF
flag has changed from 0 to 1 can also be given by the RXI
interrupt.
To continue transmitting and receiving serial data: check
the RDRF flag, read RDR, and clear the RDRF flag to 0
before the MSB (bit 7) of the current frame is received.
Also check that the TDRE flag is set to 1, indicating that
data can be written, write data in TDR, then clear the
TDRE flag to 0 before the MSB (bit 7) of the current frame
is transmitted. When the DMAC is activated by a transmit-
data-empty interrupt request (TXI) to write data in TDR,
the TDRE flag is checked and cleared automatically.
When the DMAC is activated by a receive-data-full
interrupt request (RXI) to read RDR, the RDRF flag is
cleared automatically.
Notification that the TDRE flag has changed from 0 to 1
Neither transmitting nor receiving can resume while the
Rev. 2.0, 06/04, page 509 of 980
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