HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 652

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(m) The return value in the programming program, FPFR (general register R0L) is judged.
(n) Determine whether programming of the necessary data has finished.
(o) After programming finishes, clear FKEY and specify software protection.
Erasing Procedure in User Program Mode: The procedures for download, initialization, and
erasing are shown in figure 18.12.
If more than 128 bytes of data are to be programmed, specify FMPAR and FMPDR in 128-
byte units, and repeat steps (l) to (m). Increment the programming destination address by 128
bytes and update the programming data pointer correctly. If an address which has already been
programmed is written to again, not only will a programming error occur, but also flash
memory will be damaged.
If this LSI is restarted by a power-on reset immediately after user MAT programming has
finished, secure a reset period (period of RES = 0) that is at least as long as normal 100 s.
to be downloaded and set
JSR FTDAR setting+32
Select on-chip program
Start erasing procedure
download destination
Set the FPEFEQ and
Since the stack area is used in the programming program, a stack area of a maximum
128 bytes must be reserved in RAM
FUBRA parameters
Set SCO to 1 and
execute download
Set FKEY to H'A5
Clear FKEY to 0
FPFR=0 ?
Initialization
DPFR = 0?
by FTDAR
program
1
Yes
Yes
Initialization error processing
Download error processing
No
No
(a)
Figure 18.12 Erasing Procedure
No
JSR FTDAR setting+16
Disable interrupts and
bus master operation
Set FEBS parameter
procedure program
Set FKEY to H'5A
Clear FKEY to 0
other than CPU
Rev. 2.0, 06/04, page 623 of 980
Required block
End erasing
FPFR=0 ?
completed?
erasing is
Erasing
1
Yes
Yes
Clear FKEY and erasing
No
error processing
(b)
(c)
(d)
(e)
(f)