HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 133

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4
5.4.1
The H8/3029 handles interrupts differently depending on the setting of the UE bit. When UE = 1,
interrupts are controlled by the I bit. When UE = 0, interrupts are controlled by the I and UI bits.
Table 5.4 indicates how interrupts are handled for all setting combinations of the UE, I, and UI
bits.
NMI interrupts are always accepted except in the reset and hardware standby states*. IRQ
interrupts and interrupts from the on-chip supporting modules have their own enable bits.
Interrupt requests are ignored when the enable bits are cleared to 0.
Note: * NMI input is sometimes disabled. For details see section 18.4.5, Flash Vector Address
Table 5.4
SYSCR
UE
1
0
UE = 1: Interrupts IRQ
masked by the I bit in the CPU’s CCR. Interrupts are masked when the I bit is set to 1, and
unmasked when the I bit is cleared to 0. Interrupts with priority level 1 have higher priority.
Figure 5.4 is a flowchart showing how interrupts are accepted when UE = 1.
Rev. 2.0, 06/04, page 104 of 980
Control Register (FVACR).
Interrupt Operation
Interrupt Handling Process
I
0
1
0
1
UE, I, and UI Bit Settings and Interrupt Handling
CCR
UI
—
—
—
0
1
0
to IRQ
Description
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
No interrupts are accepted except NMI.
All interrupts are accepted. Interrupts with priority level 1 have higher
priority.
NMI and interrupts with priority level 1 are accepted.
No interrupts are accepted except NMI.
5
and interrupts from the on-chip supporting modules can all be