HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 566
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Table 14.8 Smart Card Interface Mode Operating States and Interrupt Sources
Operating State
Transmit Mode
Receive Mode
Data Transfer by DMAC: The DMAC can be used to transmit and receive data in smart card
mode, as in normal SCI operations. In transmit mode, when the TEND flag is set to 1 in SSR, the
TDRE flag is set simultaneously, generating a TXI interrupt. If the TXI request is designated
beforehand as a DMAC activation source, the DMAC will be activated by the TXI request and
will transfer the next transmit data. This data transfer by the DMAC automatically clears the
TDRE and TEND flags to 0. In the event of an error, the SCI automatically retransmits the same
data, keeping the TEND flag cleared to 0 so that the DMAC is not activated. The SCI and DMAC
will therefore automatically transmit the designated number of bytes, including retransmission
when an error occurs. When an error occurs, the ERS flag is not cleared automatically, so the RIE
bit should be set to 1 to enable the error to generate an ERI request, and the ERI interrupt handler
should clear ERS.
When using the DMAC to transmit or receive, first set up and enable the DMAC, then make SCI
settings. DMAC settings are described in section 7, DMA controller.
In receive operations, an RXI interrupt is requested when the RDRF flag is set to 1 in SSR. If the
RXI request is designated beforehand as a DMAC activation source, the DMAC will be activated
by the RXI request and will transfer the received data. This data transfer by the DMAC
automatically clears the RDRF flag to 0. When an error occurs, the RDRF flag is not set and an
error flag is set instead. The DMAC is not activated. The ERI interrupt request is directed to the
CPU. The ERI interrupt handler should clear the error flags.
Normal
operation
Error
Normal
operation
Error
Flag
TEND
ERS
RDRF
PER, ORER
Enable Bit
RIE
TIE
RIE
RIE
Rev. 2.0, 06/04, page 537 of 980
Interrupt
Source
RXI
TXI
ERI
ERI
DMAC
Activation
Available
Available
Not available
Not available
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