HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 642

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

adjustment end sign (1 byte of H'00) to the host. The host must confirm that this bit adjustment
end sign (H'00) has been received normally and transmits 1 byte of H'55 to this LSI. When
reception is not executed normally, boot mode is initiated again (reset) and the operation
described above must be executed. The bit rate between the host and this LSI is not matched by
the bit rate of transmission by the host and system clock frequency of this LSI. To operate the SCI
normally, the transfer bit rate of the host must be set to 9,600 bps or 19,200 bps.
The system clock frequency which can automatically adjust the transfer bit rate of the host and the
bit rate of this LSI is shown in table 18.8. Boot mode must be initiated in the range of this system
clock.
Table 18.8 System Clock Frequency that Can Automatically Adjust Bit Rate of This LSI
Bit rate of host
9,600 bps
19,200 bps
State Transition: The overview of the state transition after boot mode is initiated is shown in
figure 18.8. For details on boot mode, refer to section 18.10.1, Serial Communications Interface
Specification for Boot Mode.
1. Bit rate adjustment
2. Waiting for inquiry set command
3. Automatic erasure of all user MAT and user boot MAT
After boot mode is initiated, the bit rate of the SCI interface is adjusted with that of the host.
For inquiries about user-MAT size and configuration, MAT start address, and support state,
the required information is transmitted to the host.
After inquiries have finished, all user MAT and user boot MAT are automatically erased.
Start
bit
Figure 18.7 Automatic Adjustment Operation of SCI Bit Rate
System clock frequency which can automatically adjust bit rate of this LSI
10 to 25 MHz
16 to 25 MHz
D0
Measure low period (9 bits) (data is H'00)
D1
D2
D3
D4
D5
D6
Rev. 2.0, 06/04, page 613 of 980
D7
Stop bit
High period of
at least 1 bit