HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 170

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.3.4
For each of areas 0 to 7, the H8/3029 can output a chip select signal (CS
when the corresponding area is selected in expanded mode. Figure 6.4 shows the output timing of
a CSn signal.
Output of CS
(DDR) of the corresponding port.
In the expanded modes with on-chip ROM disabled, a reset leaves pin CS
pins CS
DDR bits must be set to 1. In the expanded modes with on-chip ROM enabled, a reset leaves pins
CS
must be set to 1. For details, see section 8, I/O Ports.
Output of CS
register (CSCR). A reset leaves pins CS
CS
When the on-chip ROM, on-chip RAM, and on-chip registers are accessed, CS
high. The CS
signals for SRAM and other devices.
0
4
to CS
to CS
1
to CS
3
7
Chip Select Signals
, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
CS
CS
CS
in the input state. To output chip select signals CS
CS
CS
CS
n
0
4
3
signals are decoded from the address signals. They can be used as chip select
to CS
to CS
in the input state. To output chip select signals CS
CS
CS
CS
CS
CS
CS
Address
3
7
+5
: Output of CS
: Output of CS
Figure 6.4 CS
n
CS
CSn Signal Output Timing (n = 0 to 7)
CS
0
4
to CS
to CS
4
to CS
3
7
is enabled or disabled in the data direction register
is enabled or disabled in the chip select control
External address in area n
7
in the input state. To output chip select signals
0
to CS
Rev. 2.0, 06/04, page 141 of 980
1
to CS
3
, the corresponding DDR bits
0
3
to CS
0
, the corresponding
in the output state and
0
7
) that goes low
to CS
7
remain