HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 217

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.9
6.9.1
When the H8/3029 chip accesses external space, it can insert a 1-state idle cycle (T
cycles in the following cases: (1) when read accesses between different areas occur consecutively,
(2) when a write cycle occurs immediately after a read cycle, and (3) immediately after a DRAM
space access. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, which has a long output floating time, and high-speed memory, I/O interfaces, and
so on.
The ICIS1 and ICIS0 bits in BCR both have an initial value of 1, so that an idle cycle is inserted in
the initial state. If there are no data collisions, the ICIS bits can be cleared.
Consecutive Reads between Different Areas: If consecutive reads between different areas occur
while the ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.43 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM,
each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.44 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle.
Rev. 2.0, 06/04, page 188 of 980
Address bus
Idle Cycle
Operation
Data bus
4,
Figure 6.43 Example of Idle Cycle Operation (1) (ICIS1 = 1)
(a) Idle cycle not inserted
Bus cycle A Bus cycle B
T
1
T
Long buffer-off
2
T
3
time
T
1
T
2
Data
collision
Address bus
Data bus
4,
Bus cycle A Bus cycle B
T
(b) Idle cycle inserted
1
T
2
T
3
T
i
T
I
) between bus
1
T
2