HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 162

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 3—Reserved: This bit cannot be modified and is always read as 1.
Bit 2—TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (T
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles.
The setting of this bit does not affect the self-refresh function.
Bit 2
TPC
0
1
Bit 1—RAS
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
0
1
Bit 0—Refresh Cycle Wait Control (RLW): Controls wait state (T
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
0
1
6.2.9
RTMCSR is an 8-bit readable/writable register that selects the refresh timer counter clock. When
the refresh timer is used as an interval timer, RTMCSR also enables or disables interrupt requests.
Bits 7 and 6 of RTMCSR are initialized to 0 by a reset and in the standby modes. Bits 5 to 3 are
initialized to 0 by a reset and in hardware standby mode; they are not initialized in software
standby mode.
Bit
Initial value
Read/Write
RAS-CAS
RAS
RAS
Refresh Timer Control/Status Register (RTMCSR)
CAS Wait (RCW): Controls wait state (Trw) insertion between T
CAS
CAS
R(W)*
CMF
7
0
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
Description
Wait state (Trw) insertion disabled
One wait state (Trw) inserted
Description
Wait state (T
One wait state (T
CMIE
R/W
6
0
RW
) insertion disabled
RW
CKS2
R/W
) inserted
5
0
CKS1
R/W
4
0
CKS0
R/W
3
0
Rev. 2.0, 06/04, page 133 of 980
RW
—
—
) insertion for CAS-before-
2
1
r
and T
—
—
1
1
(Initial value)
(Initial value)
(Initial value)
c1
in DRAM
—
—
P
0
1
) is to