HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 96

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
3.6
Figures 3.1 and 3.2 show memory maps of the H8/3029. The address space is divided into eight
areas.
The EMC bit in BCR can be read and written to select either of the two memory maps. For details,
see section 6.2.5, Bus Control Register (BCR).
The initial bus mode differs between modes 1 and 2, and also between modes 3 and 4.
The address locations of the on-chip RAM and on-chip registers differ between the 1-Mbyte
modes (modes 1, 2, and 7), and the 16-Mbyte modes (modes 3, 4, and 5). The address range
specifiable by the CPU in the 8- and 16-bit absolute addressing modes (@aa:8 and @aa:16) also
differs.
3.6.1
The H8/3029 memory map includes reserved areas to which read/write access is prohibited. Note
that normal operation is not guaranteed if the following reserved areas are accessed.
The reserved area in the internal I/O register space.
The H8/3029 internal I/O register space includes a reserved area to which access is prohibited.
For details see appendix B, Internal I/O Registers.
Note on Reserved Areas
Memory Map in Each Operating Mode
Rev. 2.0, 06/04, page 67 of 980

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