HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 603

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
17.1.2
The on-chip RAM is controlled by SYSCR. Table 17.1 gives the address and initial value of
SYSCR.
Table 17.1 System Control Register
H'EE012
Note:
17.2
One function of SYSCR is to enable or disable access to the on-chip RAM. The on-chip RAM is
enabled or disabled by the RAME bit in SYSCR. For details about the other bits, see section 3.3,
System Control Register (SYSCR).
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized at the rising edge of the input at the RES pin. It is not initialized in software standby
mode.
1
Rev. 2.0, 06/04, page 574 of 980
Address*
Bit 0
RAME
0
Bit
Initial value
Read/Write
* Lower 20 bits of the address in advanced mode.
Register Configuration
System Control Register (SYSCR)
On-chip RAM is enabled
Description
On-chip RAM is disabled
System control register
Name
SSBY
R/W
Software standby
7
0
STS2
R/W
6
0
STS1
Standby timer select 2 to 0
R/W
5
0
STS0
R/W
4
0
SYSCR
Abbreviation
User bit enable
R/W
UE
3
1
NMIEG
R/W
NMI edge select
2
0
R/W
R/W
SSOE
Software standby
output port enable
R/W
1
0
RAM enable bit
Enables or disables
on-chip RAM
H'09
Initial Value
RAME
R/W
(Initial value)
0
1

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