HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 323

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.11.2
Table 8.18 summarizes the registers of port A.
Table 8.18 Port A Registers
Address*
H'EE009
H'FFFD9
Note:
Port A Data Direction Register (PADDR): PADDR is an 8-bit write-only register that can select
input or output for each pin in port A. When pins are used for TPC output, the corresponding
PADDR bits must also be set.
The pin functions that can be selected for pins PA
modes 3 to 5. For the method of selecting the pin functions, see tables 8.19 and 8.20.
The pin functions that can be selected for pins PA
method of selecting the pin functions, see table 8.21.
When port A functions as an input/output port, a pin in port A becomes an output port if the
corresponding PADDR bit is set to 1, and an input port if this bit is cleared to 0. In modes 3 and 4,
PA
PADDR is a write-only register. Its value cannot be read. All bits return 1 when read.
PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
Rev. 2.0, 06/04, page 294 of 980
Modes
3, 4
Modes
1, 2, 5,
and 7
Bit
7
DDR is fixed at 1 and PA
* Lower 20 bits of the address in advanced mode.
Initial value
Read/Write
Initial value
Read/Write
Register Descriptions
Name
Port A data direction
register
Port A data register
PA DDR
7
—
W
7
1
0
PA DDR
7
functions as the A
6
W
W
6
0
0
Abbreviati
on
PADDR
PADR
PA DDR
5
W
W
5
0
0
Port A data direction 7 to 0
These bits select input or output for port A pins
R/W
R/W
W
20
PA DDR
7
3
address output pin.
to PA
to PA
4
W
W
4
0
0
4
0
Modes 1, 2, 5, and 7
H'00
H'00
differ between modes 1, 2, and 7, and
are the same in modes 1 to 5, 7. For the
PA DDR
3
W
W
3
0
0
PA DDR
Initial Value
2
W
W
2
0
0
PA DDR
1
W
W
1
0
0
Modes 3, 4
H'80
H'00
PA DDR
0
W
W
0
0
0