HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 620

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 18.5 Register/Parameter and Target Mode
Programming/
erasing
interface
registers
Programming/
erasing
interface
parameter
RAM emulation
Notes: *1 The setting is required when programming or erasing user MAT in user boot mode.
18.4.2
The programming/erasing interface registers are as described below. They are all 8-bit registers
that can be accessed in byte. Except for the FLER bit in FCCS, these registers are initialized at a
power-on reset, in hardware standby mode, or in software standby mode. The FLER bit is not
initialized in software standby mode.
(1) Flash Code Control and Status Register (FCCS)
FCCS is configured by bits which request the monitor of the FWE pin state and error occurrence
during programming or erasing flash memory and the download of on-chip program.
Bit 7—Flash Programming Enable (FWE): Monitors level which is input to the FWE pin that
performs hardware protection of the flash memory programming or erasing. The initial value is 0
or 1 according to the FWE pin state.
Bit :
Initial value :
R/W :
*2 The setting may be required according to the combination of initiation mode and read
Programming/Erasing Interface Register
target MAT.
FCCS
FPCS
PECS
FKEY
FMATS
FTDAR
DPFR
FPFR
FPEFEQ
FUBRA
FMPAR
FMPDR
FEBS
RAMCR
FWE
1/0
R
7
—
Download
—
—
—
—
—
—
—
—
R
6
0
—
R
5
0
Initiali-
zation
—
—
—
—
—
—
—
—
—
—
—
FLER
R
4
0
Program-
ming
—
—
—
—
—
—
—
—
—
*
1
—
R
3
0
Rev. 2.0, 06/04, page 591 of 980
Erasure
—
—
—
—
—
—
—
—
—
—
*
1
—
R
2
0
—
Read
—
—
—
—
—
—
—
—
—
—
—
—
*
—
R
1
0
2
RAM
Emulation
—
—
—
—
—
—
—
—
—
—
—
—
—
(R)W
SCO
0
0