HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 307

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Table 8.11 Port 6 Pin Functions in Modes 1 to 5
Pin
P6
LWR
HWR
RD
AS
P6
P6
P6
Rev. 2.0, 06/04, page 278 of 980
7
2
1
0
/
/BACK
/BREQ
/WAIT
Pin Functions and Selection Method
Bit PSTOP in MSTCRH selects the pin function.
PSTOP
Pin function
Functions as LWR regardless of the setting of bit P6
P6
Pin function
Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, LWR
Functions as HWR regardless of the setting of bit P6
P6
Pin function
Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1 and bit CSEL in DRCRB is 1, HWR
Functions as RD regardless of the setting of bit P6
P6
Pin function
Note: * If any of bits DRAS2 to DRAS0 in DRCRA is 1, RD output functions as WE.
Functions as AS regardless of the setting of bit P6
P6
Pin function
Bit BRLE in BRCR and bit P6
BRLE
P6
Pin function
Bit BRLE in BRCR and bit P6
BRLE
P6
Pin function
Bit WAITE in BCR and bit P6
WAITE
P6
Pin function
Note: * Do not set bit P6
6
5
4
3
2
1
0
DDR
DDR
DDR
DDR
DDR
DDR
DDR
output functions as LCAS.
output functions as UCAS.
0
DDR to 1.
P6
P6
P6
0
2
1
DDR select the pin function as follows.
DDR select the pin function as follows.
DDR select the pin function as follows.
2
1
0
0
0
0
input
input
input
output
0
0
0
0
0
0
0
0
P6
P6
P6
2
1
0
3
output
output
output
4
DDR.
1
1
1
DDR.
6
5
DDR.
DDR.
HWR output*
LWR output*
RD output*
AS output
BACK output
BREQ input
WAIT input
P6
7
—
—
0*
1
1
1
1
1
1
1
1
input