HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 707

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

18.10.3 Procedure Program and Storable Area for Programming Data
In the descriptions in the previous section, the programming/erasing procedure programs and
storable areas for program data are assumed to be in the on-chip RAM. However, the program
and the data can be stored in and executed from other areas, such as part of flash memory which is
not to be programmed or erased, or somewhere in the external address space.
•
(1) The on-chip programming/erasing program is downloaded from the address set by FTDAR in
(2) The on-chip programming/erasing program will use the 128 bytes as a stack. So, make sure
(3) Since download by setting the SCO bit to 1 will cause the MATs to be switched, it should be
(4) The flash memory is accessible until the start of programming or erasing, that is, until the
(5) The flash memory is not accessible during programming/erasing operations, therefore, the
(6) After programming/erasing, the flash memory should be inhibited until FKEY is cleared.
Rev. 2.0, 06/04, page 678 of 980
Conditions that Apply to Programming/Erasing
on-chip RAM, therefore, this area is not available for use.
that this area is secured.
executed in on-chip RAM.
result of downloading has been judged. When in a mode in which the external address space
is not accessible, such as single-chip mode, the required procedure programs, NMI handling
vector, NMI handler and user branch program should be transferred to the on-chip RAM
before programming/erasing of the flash memory starts.
operation program is downloaded to the on-chip RAM to be executed. The NMI-handling
vector and programs such as that which activate the operation program, user program at the
user-branch destination during programming/erasing operation, and NMI handler should thus
be stored in on-chip memory other than flash memory or the external address space.
The reset state (RES = 0) must be in place for more than 100 s when the LSI mode is
changed to reset on completion of a programming/erasing operation.
Note: Set the FWE input pin low level, except in the auto-program and auto-erase modes.
4-5
FWE
V
CC
Figure 18.36 Oscillation Stabilization Time, PROM Mode Setup Time, and
t
osc1
t
bmv
Memory read mode
Command wait state
Power-Down Sequence
Auto-program mode
Auto-erase mode
Command wait state
Normal/abnormal
end identification
t
dwn