HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 365

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bits 6 and 5—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select how 16TCNT is
cleared.
Bit 6
CCLR1
0
1
Notes: *1 16TCNT is cleared by compare match when the general register functions as an output
Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select external clock input
edges when an external clock source is used.
Bit 4
CKEG1
0
1
When channel 2 is set to phase counting mode, bits CKEG1 and CKEG0 in 16TCR2 are ignored.
Phase counting takes precedence.
Bits 2 to 0—Timer Prescaler 2 to 0 (TPSC2 to TPSC0): These bits select the counter clock of
16TCNT.
Bit 2
TPSC2
0
1
Rev. 2.0, 06/04, page 336 of 980
*2 Selected in TSNC.
Bit 3
CKEG0
0
1
—
Bit 1
TPSC1
0
1
0
1
Bit 5
CCLR0
0
1
0
1
compare register, and by input capture when the general register functions as an input
capture register.
Description
16TCNT is not cleared
16TCNT is cleared by GRA compare match or input capture*
16TCNT is cleared by GRB compare match or input capture*
Synchronous clear: 16TCNT is cleared in synchronization with other
synchronized timers*
Description
Count rising edges
Count falling edges
Count both edges
Bit 0
TPSC0
0
1
0
1
0
1
0
1
Function
Internal clock:
Internal clock: /2
Internal clock: /4
Internal clock: /8
External clock A: TCLKA input
External clock B: TCLKB input
External clock C: TCLKC input
External clock D: TCLKD input
2
1
1
(Initial value)
(Initial value)
(Initial value)