HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 237

MCU 5V 512K,PB-FREE 100-TQFP

HD64F3029XBL25V

Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet

Specifications of HD64F3029XBL25V

Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
7.3
In full address mode the A and B channels operate together. Full address mode is selected as
indicated in table 7.4.
7.3.1
A memory address register (MAR) is a 32-bit readable/writable register. MARA functions as the
source address register of the transfer, and MARB as the destination address register.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1. (Write is invalid.)
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.3.2
The I/O address registers (IOARs) are not used in full address mode.
Rev. 2.0, 06/04, page 208 of 980
Bit
Initial value
Read/Write
Register Descriptions (2) (Full Address Mode)
Memory Address Registers (MAR)
31
I/O Address Registers (IOAR)
30
29
MARR
28
27
26
25
24
R/W
23
R/W
22
R/W
21
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
R/W
17
Undetermined
R/W
16
R/W
15
R/W
14
R/W
13
R/W
MARH
12
R/W
11
R/W
10
R/W
9
R/W
8
R/W
7
R/W
6
R/W
5
R/W
MARL
4
R/W
3
R/W
2
R/W
1
R/W
0

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