HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 273

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4.10
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer
of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus
right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a
burst transfer on channel 0.
Rev. 2.0, 06/04, page 244 of 980
Address
bus
RD
HWR
LWR
Address
bus
RD
HWR LWR
,
,
External Bus Requests, DRAM Interface, and DMAC
DMAC cycle
(channel 1)
T
1
T
Figure 7.20 Bus Timing of DRAM Interface, and DMAC
1
T
Figure 7.19 Timing of Multiple-Channel Operations
2
DMAC cycle (channel 0)
T
2
T
1
T
1
T
CPU
cycle
2
T
2
T
1
T
d
T
2
T
1
DMAC cycle
(channel 0A)
T
1
T
2
T
2
T
T
1
Refresh
cycle
1
T
T
2
2
T
T
1
d
CPU
cycle
T
T
DMAC cycle (channel 0)
2
1
T
T
d
2
T
T
1
1
DMAC cycle
(channel 1)
T
T
2
2
T
T
1
1
T
T
2
2