HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 290

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

8.3
8.3.1
Port 2 is an 8-bit input/output port also used for address output, with the pin configuration shown
in figure 8.2. The pin functions differ according to the operating mode.
In modes 1 to 4 (expanded modes with on-chip ROM disabled), port 2 consists of address bus
output pins (A
port 2 data direction register (P2DDR) can designate pins for address bus output (A
generic input. In mode 7 (single-chip mode), port 2 is a generic input/output port.
When DRAM is connected to areas 2 to 5, A
write cycles. For details see section 6.5, DRAM Interface.
Port 2 has software-programmable built-in pull-up transistors.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive an LED or
a darlington transistor pair.
Port 2
Port 2
Overview
15
to A
8
Port 2 pins
). In mode 5 (expanded mode with on-chip ROM enabled), settings in the
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
P2 /A
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Figure 8.2 Port 2 Pin Configuration
Modes 1 to 4
A
A
A
A
A
A
A (output)
A (output)
15
14
13
12
11
10
9
8
(output)
(output)
(output)
(output)
(output)
(output)
12
to A
8
Mode 5
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
P2 (input)/A
output row and column addresses in read and
7
6
5
4
3
2
1
0
15
14
13
12
11
10
9
8
Rev. 2.0, 06/04, page 261 of 980
(output)
(output)
(output)
(output)
(output)
(output)
(output)
(output)
Mode 7
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
P2 (input/output)
7
6
5
4
3
2
1
0
15
to A
8
) or