HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 219

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Usage Notes: When non-insertion of idle cycles is set, the rise (negation) of RD and the fall
(assertion) of CSn may occur simultaneously. An example of the operation is shown in figure
6.47.
If consecutive reads between different external areas occur while the ICIS1 bit is cleared to 0 in
BCR, or if a write cycle to a different external area occurs after an external read while the ICIS0
bit is cleared to 0, the RD negation in the first read cycle and the CSn assertion in the following
bus cycle will occur simultaneously. Therefore, depending on the output delay time of each signal,
it is possible that the low-level output of RD in the preceding read cycle and the low-level output
of CSn in the following bus cycle will overlap.
A setting whereby idle cycle insertion is not performed can be made only when RD and CSn do
not change simultaneously, or when it does not matter if they do.
Rev. 2.0, 06/04, page 190 of 980
(
Address bus
Figure 6.45 Example of Idle Cycle Operation (3) (HWR
Figure 6.46 Example of Idle Cycle Operation (4) (Consecutive Precharge Cycles)
/
/
)
(a) Idle cycle not inserted
(DRAM access cycle)
Tp
Bus cycle A
Address bus
Address bus
Tr Tc1 Tc2
/
Simultaneous change of
/
Bus cycle B
T1
and
T1
External read
T2
T2
(
T3
Address bus
Tp
/
DRAM space read
/
HWR
HWR
HWR/LWR
Tr
)
(DRAM access cycle) Bus cycle B
LWR
LWR Used as UCAS
Tc1
LWR
Tp
Bus cycle A
(b) Idle cycle inserted
Tc2
Tr Tc1 Tc2
UCAS
UCAS
UCAS/LCAS
Ti
LCAS
LCAS)
LCAS
T1
T2