HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 553
HD64F3029XBL25V
Manufacturer Part Number
HD64F3029XBL25V
Description
MCU 5V 512K,PB-FREE 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Datasheet
1.HD64F3029X25.pdf
(1012 pages)
Specifications of HD64F3029XBL25V
Core Processor
H8/300H
Core Size
16-Bit
Speed
25MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
70
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Bit 6: Only 0 should be written to this bit.
Bits 5 to 2: These bits operate as in normal serial communication. For details see section 13.2.5,
Serial Mode Register (SMR).
Bits 1 and 0: Only 0 should be written to these bits.
14.2.4
The function of SCR bits 1 and 0 is modified in smart card interface mode
Bits 7 to 2: These bits operate as in normal serial communication. For details see section 13.2.6,
Serial Control Register (SCR).
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits select the SCI clock source and
enable or disable clock output from the SCK pin. In smart card interface mode, it is possible to
specify a fixed high level or fixed low level for the clock output, in addition to the usual switching
between enabling and disabling of the clock output.
Bit 7
GM
0
1
14.3
14.3.1
The main features of the smart card interface are as follows.
Rev. 2.0, 06/04, page 524 of 980
Bit
Initial value
Read/Write
One frame consists of 8-bit data plus a parity bit.
Serial Control Register (SCR)
Operation
Overview
Bit 1
CKE1
0
1
R/W
TIE
7
0
Bit 0
CKE0
0
1
0
1
0
1
R/W
RIE
6
0
Description
Internal clock/SCK pin is I/O port
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at low output
Internal clock/SCK pin is clock output
Internal clock/SCK pin is fixed at high output
Internal clock/SCK pin is clock output
R/W
TE
5
0
R/W
RE
4
0
MPIE
R/W
3
0
TEIE
R/W
2
0
CKE1
R/W
1
0
(Initial value)
CKE0
R/W
0
0
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