HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 718

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.1
The H8/3029 has a built-in clock pulse generator (CPG) that generates the system clock ( ) and
other internal clock signals ( /2 to /4096). After duty adjustment, a frequency divider divides the
clock frequency to generate the system clock ( ). The system clock is output at the pin*
furnished as a master clock to prescalers that supply clock signals to the on-chip supporting
modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the frequency
divider by settings in a division control register (DIVCR)*
reduced in almost direct proportion to the frequency division ratio.
Notes: *1 Usage of the pin differs depending on the chip operating mode and the PSTOP bit
19.1.1
Figure 19.1 shows a block diagram of the clock pulse generator.
*2 The division ratio of the frequency divider can be changed dynamically during
Overview
Block Diagram
XTAL
EXTAL
setting in the module standby control register (MSTCR). For details, see section 20.7,
System Clock Output Disabling Function.
operation. The clock output at the pin also changes when the division ratio is
changed. The frequency output at the pin is shown below.
where, EXTAL: Frequency of crystal resonator or external clock signal
n:
= EXTAL
Figure 19.1 Block Diagram of Clock Pulse Generator
Section 19 Clock Pulse Generator
Oscillator
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
n
adjustment
circuit
Duty
Frequency
Data bus
2
Division
register
. Power consumption in the chip is
divider
control
Rev. 2.0, 06/04, page 689 of 980
pin
Prescalers
/2 to /4096
CPG
1
and