HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 152

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.2.4
BRCR is an 8-bit readable/writable register that enables address output on bus lines A
enables or disables release of the bus to an external device.
BRCR is initialized to H'FE in modes 1, 2, 5, and 7, and to H'EE in modes 3 and 4, by a reset and
in hardware standby mode. It is not initialized in software standby mode.
Bit 7—Address 23 Enable (A23E): Enables PA
Writing 0 in this bit enables A
be modified and PA
Bit 7
A23E
0
1
Bit 6—Address 22 Enable (A22E): Enables PA
Writing 0 in this bit enables A
be modified and PA
Bit 6
A22E
0
1
Bit
Modes
1, 2,
and 7
Modes
3 and 4
Mode 5
Initial value
Read/Write
Initial value
Read/Write
Initial value
Read/Write
Bus Release Control Register (BRCR)
Description
PA
PA
Description
PA
PA
4
5
A23E
R/W
R/W
has its ordinary port functions.
has its ordinary port functions.
Address 23 to 20 enable
These bits enable PA
used for A
—
7
1
1
1
4
4
5
5
is the A
is an input/output pin
is the A
is an input/output pin
23
22
A22E
R/W
R/W
23
23
22
—
output from PA
output from PA
6
1
1
1
address output pin
address output pin
to A
20
A21E
address output
R/W
R/W
—
5
1
1
1
7
to PA
4
5
4
. In modes other than 3, 4, and 5, this bit cannot
. In modes other than 3, 4, and 5, this bit cannot
4
5
A20E
to be
R/W
to be used as the A
to be used as the A
—
—
4
1
0
1
—
—
—
—
3
1
1
1
Reserved bits
Rev. 2.0, 06/04, page 123 of 980
23
22
—
—
—
—
2
1
1
1
address output pin.
address output pin.
Bus release enable
Enables or disables
release of the bus
to an external device
—
—
—
—
1
1
1
1
(Initial value)
(Initial value)
23
BRLE
to A
R/W
R/W
R/W
0
0
0
0
20
and