HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 342

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.1
The H8/3029 has built-in 16-bit timer module with three 16-bit counter channels.
9.1.1
16-bit timer features are listed below.
Capability to process up to 6 pulse outputs or 6 pulse inputs
Six general registers (GRs, two per channel) with independently-assignable output compare or
input capture functions
Selection of eight counter clock sources for each channel:
Internal clocks: , /2, /4, /8
External clocks: TCLKA, TCLKB, TCLKC, TCLKD
Five operating modes selectable in all channels:
Phase counting mode selectable in channel 2
Two-phase encoder output can be counted automatically.
High-speed access via internal 16-bit bus
The 16TCNTs and GRs can be accessed at high speed via a 16-bit bus.
Any initial timer output value can be set
Nine interrupt sources
Each channel has two compare match/input capture interrupts and an overflow interrupt. All
interrupts can be requested independently.
Waveform output by compare match
Selection of 0 output, 1 output, or toggle output (only 0 or 1 output in channel 2)
Input capture function
Rising edge, falling edge, or both edges (selectable)
Counter clearing function
Counters can be cleared by compare match or input capture.
Synchronization
Two or more timer counters (16TCNTs) can be preset simultaneously, or cleared
simultaneously by compare match or input capture. Counter synchronization enables
synchronous register input and output.
PWM mode
PWM output can be provided with an arbitrary duty cycle. With synchronization, up to
three-phase PWM output is possible.
Overview
Features
Section 9 16-Bit Timer
Rev. 2.0, 06/04, page 313 of 980