HD64F3029XBL25V Renesas Electronics America, HD64F3029XBL25V Datasheet - Page 161

• Manufacturer Part Number: HD64F3029XBL25V
• Description: MCU 5V 512K,PB-FREE 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of HD64F3029XBL25V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 25MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 70
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 7
MXC1
0
1
Bit 5—CAS
to 5 are designated as DRAM space.
Bit 5
CSEL
0
1
Bit 4—Refresh Cycle Enable (RCYCE): Enables or disables CAS-before-RAS refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
0
1
Rev. 2.0, 06/04, page 132 of 980
CAS
CAS Output Pin Select (CSEL): Selects the UCAS and LCAS output pins when areas 2
CAS
Bit 6
MXC0
0
1
0
1
Description
Column address: 8 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
Column address: 9 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
Column address: 10 bits
Compared address:
Modes 1, 2
Modes 3, 4, 5
Illegal setting
Description
PB4 and PB5 selected as UCAS and LCAS output pins
HWR and LWR selected as UCAS and LCAS output pins
Description
Refresh cycles disabled
DRAM refresh cycles enabled
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
8-bit access space
16-bit access space
A
A
A
A
A
A
A
A
A
A
A
A
19
19
23
23
19
19
23
23
19
19
23
23
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
to A
8
9
8
9
9
10
9
10
10
11
10
11
(Initial value)
(Initial value)